--- a/gsm-fw/bsp/rtc/rtc_functions.c	Mon Nov 18 00:08:43 2013 +0000
+++ b/gsm-fw/bsp/rtc/rtc_functions.c	Mon Nov 18 00:52:05 2013 +0000
@@ -178,11 +178,13 @@
 
 extern T_RTC_ENV_CTRL_BLK* rtc_env_ctrl_blk;
 
+#if CONFIG_GSM
 /* Number of 32 Khz clock */
 static UINT32 rtc_nb_32khz = 0;
 
 /* Number of high frequency clock */
 static UINT32 rtc_nb_hf = 0;
+#endif
 
 static NU_HISR hisr;
 char hisrStack[512];
@@ -340,16 +342,33 @@
 
    /* Enable IRQ9 and IRQ10 */
    #if (CHIPSET == 12)
-     F_INTH_ENABLE_ONE_IT(C_INTH_RTC_TIMER_IT);
      F_INTH_ENABLE_ONE_IT(C_INTH_RTC_ALARM_IT);
    #else
-     IQ_Unmask(IQ_RTC_TIMER);
      IQ_Unmask(IQ_RTC_ALARM);
    #endif
 
+   /*
+    * FreeCalypso change: the RTC periodic interrupt is used in
+    * conjunction with the ULPD gauging mechanism, and the latter
+    * appears to be controlled by some code in L1-land.
+    * Therefore, we are going to enable this interrupt only when
+    * building with L1 enabled.
+    */
+#if CONFIG_GSM
+   #if (CHIPSET == 12)
+     F_INTH_ENABLE_ONE_IT(C_INTH_RTC_TIMER_IT);
+   #else
+     IQ_Unmask(IQ_RTC_TIMER);
+   #endif
+#endif
+
    while (RTC_TEST_BUSY);
    RTC_SET_EVENT_TIMER(RTC_EVERY_MIN); /* Set timer every minute */
+#if CONFIG_GSM
    RTC_ENABLE_IT_TIMER;
+#else
+   RTC_DISABLE_IT_TIMER;
+#endif
    RTC_DISABLE_IT_ALARM;
 
    rvf_enable();
@@ -671,7 +690,7 @@
       return FALSE;
 }
 
-
+#if CONFIG_GSM
 /*******************************************************************************
  *
  *                               RTC_ItTimerHandle
@@ -726,7 +745,7 @@
 /*NU_Activate_HISR(&hisr); tmp*/
 
 }
-
+#endif
 
 /*******************************************************************************
  *
@@ -747,6 +766,7 @@
    RTC_FREE_AL_ITLINE;
 }
 
+#if CONFIG_GSM
 /*******************************************************************************
  *
  *                               RTC_GaugingHandler
@@ -763,7 +783,7 @@
    rtc_nb_hf =   ( ((*(volatile UINT16 *)ULDP_COUNTER_HI_FREQ_MSB_REG) * 0x10000) +
             (*(volatile UINT16 *)ULDP_COUNTER_HI_FREQ_LSB_REG) );
 }
-
+#endif
 
 /*******************************************************************************
  *