FreeCalypso > hg > freecalypso-tools

annotate target-utils/simagent/simup.c @ 770:81f9e4b4f55c

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simagent: beginning of sim-up command
author Mychaela Falconia <falcon@freecalypso.org>
date Fri, 12 Mar 2021 20:11:39 +0000
parents
children 130c46b83760
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770
81f9e4b4f55c simagent: beginning of sim-up command
Mychaela Falconia <falcon@freecalypso.org>
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1 #include <sys/types.h>
81f9e4b4f55c simagent: beginning of sim-up command
Mychaela Falconia <falcon@freecalypso.org>
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2 #include <strings.h>
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Mychaela Falconia <falcon@freecalypso.org>
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3 #include "types.h"
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Mychaela Falconia <falcon@freecalypso.org>
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4 #include "abbdefs.h"
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Mychaela Falconia <falcon@freecalypso.org>
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5 #include "simregs.h"
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6
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Mychaela Falconia <falcon@freecalypso.org>
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7 #define WAIT_ONE_TDMA 60000
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8
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Mychaela Falconia <falcon@freecalypso.org>
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9 extern u16 abb_reg_read();
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Mychaela Falconia <falcon@freecalypso.org>
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10 extern void abb_reg_write();
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Mychaela Falconia <falcon@freecalypso.org>
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11
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Mychaela Falconia <falcon@freecalypso.org>
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12 int sim_if_state;
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Mychaela Falconia <falcon@freecalypso.org>
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13 u16 conf1_reg;
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Mychaela Falconia <falcon@freecalypso.org>
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14
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Mychaela Falconia <falcon@freecalypso.org>
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15 void
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Mychaela Falconia <falcon@freecalypso.org>
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16 cmd_sim_up(argbulk)
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Mychaela Falconia <falcon@freecalypso.org>
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17 char *argbulk;
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Mychaela Falconia <falcon@freecalypso.org>
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18 {
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Mychaela Falconia <falcon@freecalypso.org>
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19 char *argv[2];
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Mychaela Falconia <falcon@freecalypso.org>
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20 u16 abb_sim_reg;
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Mychaela Falconia <falcon@freecalypso.org>
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21 unsigned count;
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Mychaela Falconia <falcon@freecalypso.org>
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22
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Mychaela Falconia <falcon@freecalypso.org>
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23 if (sim_if_state) {
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Mychaela Falconia <falcon@freecalypso.org>
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24 printf("ERROR: SIM interface is already up\n");
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Mychaela Falconia <falcon@freecalypso.org>
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25 return;
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Mychaela Falconia <falcon@freecalypso.org>
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26 }
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Mychaela Falconia <falcon@freecalypso.org>
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27 if (parse_args(argbulk, 1, 1, argv, 0) < 0)
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Mychaela Falconia <falcon@freecalypso.org>
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28 return;
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Mychaela Falconia <falcon@freecalypso.org>
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29 if (!strcmp(argv[0], "1.8"))
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Mychaela Falconia <falcon@freecalypso.org>
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30 abb_sim_reg = 2;
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Mychaela Falconia <falcon@freecalypso.org>
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31 else if (!strcmp(argv[0], "3"))
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Mychaela Falconia <falcon@freecalypso.org>
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32 abb_sim_reg = 3;
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Mychaela Falconia <falcon@freecalypso.org>
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33 else {
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Mychaela Falconia <falcon@freecalypso.org>
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34 printf("ERROR: \"1.8\" or \"3\" argument expected\n");
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Mychaela Falconia <falcon@freecalypso.org>
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35 return;
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Mychaela Falconia <falcon@freecalypso.org>
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36 }
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Mychaela Falconia <falcon@freecalypso.org>
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37 abb_reg_write(VRPCSIM, abb_sim_reg);
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Mychaela Falconia <falcon@freecalypso.org>
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38 sim_if_state = 1;
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39
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40 /* wait for regulator like TI's SIM_StartVolt() */
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Mychaela Falconia <falcon@freecalypso.org>
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41 for (count = 0; ; ) {
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Mychaela Falconia <falcon@freecalypso.org>
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42 abb_sim_reg = abb_reg_read(VRPCSIM);
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Mychaela Falconia <falcon@freecalypso.org>
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43 if (abb_sim_reg & 4)
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Mychaela Falconia <falcon@freecalypso.org>
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44 break;
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Mychaela Falconia <falcon@freecalypso.org>
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45 if (++count >= 5) {
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Mychaela Falconia <falcon@freecalypso.org>
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46 printf("ERROR: VRSIM is not in proper regulation\n");
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Mychaela Falconia <falcon@freecalypso.org>
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47 return;
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Mychaela Falconia <falcon@freecalypso.org>
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48 }
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Mychaela Falconia <falcon@freecalypso.org>
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49 wait_ARM_cycles(WAIT_ONE_TDMA);
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Mychaela Falconia <falcon@freecalypso.org>
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50 }
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Mychaela Falconia <falcon@freecalypso.org>
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51
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Mychaela Falconia <falcon@freecalypso.org>
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52 /* TI's SIM_ManualStart() code follows */
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Mychaela Falconia <falcon@freecalypso.org>
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53 SIMREGS.conf1 = conf1_reg = 0x8004;
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Mychaela Falconia <falcon@freecalypso.org>
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54 SIMREGS.cmd = SIM_CMD_CLKEN;
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55
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56 SIMREGS.cmd = SIM_CMD_CLKEN | SIM_CMD_STOP;
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Mychaela Falconia <falcon@freecalypso.org>
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57 wait_ARM_cycles(WAIT_ONE_TDMA * 4);
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Mychaela Falconia <falcon@freecalypso.org>
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58
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Mychaela Falconia <falcon@freecalypso.org>
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59 SIMREGS.cmd = SIM_CMD_CLKEN | SIM_CMD_SWRST;
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Mychaela Falconia <falcon@freecalypso.org>
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60 wait_ARM_cycles(WAIT_ONE_TDMA);
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Mychaela Falconia <falcon@freecalypso.org>
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61
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Mychaela Falconia <falcon@freecalypso.org>
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62 SIMREGS.conf2 = 0x0940;
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63
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64 //enter in manual mode to start the ATR sequence
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65 SIMREGS.conf1 = conf1_reg |= SIM_CONF1_BYPASS;
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66 wait_ARM_cycles(WAIT_ONE_TDMA);
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67
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68 SIMREGS.conf1 = conf1_reg |= SIM_CONF1_SVCCLEV;
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69 wait_ARM_cycles(WAIT_ONE_TDMA);
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Mychaela Falconia <falcon@freecalypso.org>
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70
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Mychaela Falconia <falcon@freecalypso.org>
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71 abb_sim_reg |= 8;
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Mychaela Falconia <falcon@freecalypso.org>
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72 abb_reg_write(VRPCSIM, abb_sim_reg);
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Mychaela Falconia <falcon@freecalypso.org>
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73 wait_ARM_cycles(WAIT_ONE_TDMA);
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Mychaela Falconia <falcon@freecalypso.org>
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74
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Mychaela Falconia <falcon@freecalypso.org>
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75 SIMREGS.conf1 = conf1_reg &= ~SIM_CONF1_SIOLOW;
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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76 wait_ARM_cycles(WAIT_ONE_TDMA);
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Mychaela Falconia <falcon@freecalypso.org>
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77
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78 SIMREGS.conf1 = conf1_reg |= SIM_CONF1_SCLKEN;
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Mychaela Falconia <falcon@freecalypso.org>
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79 SIMREGS.conf1 = conf1_reg &= ~SIM_CONF1_TXRX; //set to receive mode
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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80 wait_ARM_cycles(WAIT_ONE_TDMA * 3);
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Mychaela Falconia <falcon@freecalypso.org>
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81
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Mychaela Falconia <falcon@freecalypso.org>
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82 /* flush any garbage in the Rx FIFO */
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Mychaela Falconia <falcon@freecalypso.org>
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83 for (count = 0; ; ) {
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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84 if (SIMREGS.stat & SIM_STAT_FEMPTY)
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Mychaela Falconia <falcon@freecalypso.org>
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85 break;
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Mychaela Falconia <falcon@freecalypso.org>
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86 (void) SIMREGS.drx;
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Mychaela Falconia <falcon@freecalypso.org>
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87 if (++count >= 32) {
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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88 printf("ERROR: Rx FIFO flush does not end\n");
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Mychaela Falconia <falcon@freecalypso.org>
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89 return;
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Mychaela Falconia <falcon@freecalypso.org>
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90 }
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Mychaela Falconia <falcon@freecalypso.org>
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91 }
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Mychaela Falconia <falcon@freecalypso.org>
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92
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Mychaela Falconia <falcon@freecalypso.org>
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93 #if 0
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Mychaela Falconia <falcon@freecalypso.org>
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94 /* lift the card out of reset! */
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Mychaela Falconia <falcon@freecalypso.org>
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95 SIMREGS.conf1 = conf1_reg |= SIM_CONF1_SRSTLEV;
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Mychaela Falconia <falcon@freecalypso.org>
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96 #endif
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Mychaela Falconia <falcon@freecalypso.org>
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97 }