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comparison chipsetsw/system/template/gsm_ds_k5a3281_big.template @ 22:89f63833708e

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RVT memory size drastically increased, now almost no loss with ext LCD out
author Space Falcon <falcon@ivan.Harhan.ORG>
date Sun, 06 Sep 2015 23:33:47 +0000
parents chipsetsw/system/template/gsm_ds_k5a3281_2092.template@a0c4fd5c7430
children
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21:be8bbcbf2163 22:89f63833708e
1 /*
2 * Integrated Protocol Stack Linker command file (all components)
3 *
4 * Target : ARM
5 *
6 * Copyright (c) Texas Instruments 2002, Condat 2002
7 *
8 * This version of the linker script template has been concocted
9 * by Spacefalcon the Outlaw, based on gsm_ds_amd8_lj3.template,
10 * in order to build the GSM firmware for the memory configuration
11 * found in the Openmoko GTA0x GSM modem, which consists of the
12 * K5A3281 flash+RAM MCP plus the 512 KiB of internal RAM in the
13 * Calypso (PD751992A) chip itself.
14 *
15 * More recent revision: the present version has been concocted in order to
16 * squeeze TI's pdt_2092 configuration (on-board UI enabled) into the same
17 * small physical memory config, with the additional complication that we need
18 * a lot of RAM for our enlargement of RVT's memory bank which is in turn
19 * needed for our external LCD output hack. We will probably have to use
20 * this linker script version for pdt_2091 built in this tree as well,
21 * as it's too difficult to conditionalize the RVT enlargement on pdt_2092.
22 */
23
24 -c /* Autoinitialize variables at runtime */
25
26 /*********************************/
27 /* SPECIFY THE SYSTEM MEMORY MAP */
28 /*********************************/
29
30 MEMORY
31 {
32 /* CS0: Flash 4 Mbytes ****************************************************/
33 /* Interrupt Vectors Table */
34 I_MEM (RXI) : org = 0x00000000 len = 0x00000100
35
36 /* Boot Sector */
37 B_MEM (RXI) : org = 0x00000100 len = 0x00001f00
38
39 /* Magic Word for Calypso Boot ROM */
40 MWC_MEM (RXI) : org = 0x00002000 len = 0x00000004 fill = 0x0000001
41
42 /* Program Memory */
43 P_MEM1 (RXI) : org = 0x00004000 len = 0x00000700
44 P_MEM2 (RXI) : org = 0x00004700 len = 0x00000004
45 P_MEM3 (RXI) : org = 0x00004704 len = 0x0037b8fc
46
47 /* FFS Area */
48 FFS_MEM (RX) : org = 0x00380000 len = 0x00080000
49 /**************************************************************************/
50
51 /* CS1: External SRAM 1 Mbytes ********************************************/
52 /* Data Memory */
53
54 /*
55 *** HACK by Spacefalcon the Outlaw ***
56 *
57 * The starting Leonardo version (gsm_ds_amd8_lj3.template) had two
58 * external SRAM regions: D_MEM1 and D_MEM2. When I tried removing
59 * D_MEM2 and keeping only D_MEM1, the linker started behaving oddly
60 * in that the sections were emitted in the wrong order, and the
61 * addresses printed in the map file were bogus. The resulting m0
62 * images seemed to still work correctly, but I feel that having the
63 * linker act "correctly" is better.
64 *
65 * My original hack-solution was to split the 1 MiB physical XRAM
66 * into D_MEM1 and D_MEM2 of 512 KiB each. As it happens, the total
67 * XRAM usage of the standard pdt_2091 firmware is a little below
68 * 512 KiB anyway.
69 *
70 * Revision for pdt_2092 memory usage: D_MEM2 is now the last 64 KiB
71 * and D_MEM1 is the rest.
72 */
73
74 D_MEM1 (RW) : org = 0x01000000 len = 0x000F0000
75 D_MEM2 (RW) : org = 0x010F0000 len = 0x00010000
76 /**************************************************************************/
77
78 /* CS6: Calypso Internal SRAM 512 kbytes **********************************/
79 /* Code & Variables Memory */
80 S_MEM (RXW) : org = 0x00800000 len = 0x00080000
81 /**************************************************************************/
82 }
83
84 /***********************************************/
85 /* SPECIFY THE SECTIONS ALLOCATION INTO MEMORY */
86 /***********************************************/
87
88 /*
89 * Since the bootloader directly calls the INT_Initialize() routine located
90 * in int.s, this int.s code must always be mapped at the same address
91 * (usually in the second flash sector). Its length is about 0x500 bytes.
92 * Then comes the code that need to be loaded into the internal RAM.
93 */
94
95 SECTIONS
96 {
97 .intvecs : {} > I_MEM /* Interrupt Vectors Table */
98 .monitor : > B_MEM /* Monitor Constants & Code */
99 {
100 $(CONST_BOOT_LIB)
101 }
102
103 .inttext : {} > P_MEM1 /* int.s Code */
104
105 .bss_dar : > D_MEM1 /* DAR SWE Variables */
106 {
107 $(BSS_DAR_LIB)
108 }
109
110 /*
111 * The .bss section should not be split to ensure it is initialized to 0
112 * each time the SW is reset. So the whole .bss is mapped either in D_MEM1
113 * or in D_MEM2.
114 *
115 * Falcon's note for K5A3281: see the comments above where the memory
116 * regions are defined.
117 */
118
119 .bss : > D_MEM1 | D_MEM2 /* Global & Static Variables */
120 {
121 $(BSS_BOOT_LIB)
122 }
123
124 /*
125 * All .bss sections, which must be mapped in internal RAM must be
126 * grouped in order to initialized the corresponding memory to 0.
127 * This initialization is done in int.s file before calling the Nucleus
128 * routine.
129 */
130
131 GROUP
132 {
133 S_D_Mem /* Label of start address of .bss section in Int. RAM */
134 .DintMem
135 {
136
137 /*
138 * .bss sections of the application
139 */
140
141 $(BSS_LIBS)
142
143 }
144
145 API_HISR_stack : {}
146
147 E_D_Mem /* Label of end address of .bss section in Int. RAM */
148 } > S_MEM
149
150 /*
151 * .text and .const sections which must be mapped in internal RAM.
152 */
153
154 .ldfl : {} > P_MEM2 /* Used to know the start load address */
155 GROUP load = P_MEM3, run = S_MEM
156 {
157 S_P_Mem /* Label of start address of .text & .const sections in Int. RAM */
158 .PIntMem
159 {
160 /*
161 * .text and .const sections of the application.
162 *
163 * The .veneer sections correspond exactly to .text:v&n sections
164 * implementing the veneer functions. The .text:v$n -> .veneer
165 * translation is performed by PTOOL software when PTOOL_OPTIONS
166 * environement variable is set to veneer_section.
167 */
168
169 $(CONST_LIBS)
170
171 }
172 E_P_Mem /* Label of end address of .text and .const sections in Int. RAM */
173 }
174
175 /*
176 * The rest of the code is mapped in flash, however the trampolines
177 * load address should be consistent with .text.
178 */
179 COMMENT2START
180 `trampolines load = P_MEM3, run = S_MEM
181 COMMENT2END
182
183 .text : {} > P_MEM3 /* Code */
184
185 /*
186 * The rest of the constants is mapped in flash.
187 * The .cinit section should not be split.
188 */
189
190 .cinit : {} > P_MEM3 /* Initialization Tables */
191 .const : {} > P_MEM3 /* Constant Data */
192 KadaAPI : {} > P_MEM3 /* ROMized CLDC */
193
194 .javastack: {} >> D_MEM1 | D_MEM2 /* Java stack */
195
196 .stackandheap : > D_MEM1 /* System Stacks, etc... */
197 {
198 /* Leave 20 32bit words for register pushes. */
199 . = align(8);
200 . += 20 * 4;
201
202 /* Stack for abort and/or undefined modes. */
203 exception_stack = .;
204
205 /* Leave 38 32bit words for state saving on exceptions. */
206 _xdump_buffer = .;
207 . += 38 * 4;
208 . = align(8);
209
210 /* Beginning of stacks and heap area - 2.75 kbytes (int.s) */
211 stack_segment = .;
212 . += 0xB00;
213 }
214
215 .data : {} > D_MEM1 /* Initialized Data */
216 .sysmem : {} > D_MEM1 /* Dynamic Memory Allocation Area */
217
218 }