FreeCalypso > hg > leo2moko-debug
annotate chipsetsw/system/template/gsm_ds_k5a3281_big.template @ 22:89f63833708e
RVT memory size drastically increased, now almost no loss with ext LCD out
author | Space Falcon <falcon@ivan.Harhan.ORG> |
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date | Sun, 06 Sep 2015 23:33:47 +0000 |
parents | chipsetsw/system/template/gsm_ds_k5a3281_2092.template@a0c4fd5c7430 |
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1 /* |
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2 * Integrated Protocol Stack Linker command file (all components) |
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3 * |
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4 * Target : ARM |
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5 * |
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6 * Copyright (c) Texas Instruments 2002, Condat 2002 |
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7 * |
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8 * This version of the linker script template has been concocted |
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9 * by Spacefalcon the Outlaw, based on gsm_ds_amd8_lj3.template, |
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10 * in order to build the GSM firmware for the memory configuration |
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11 * found in the Openmoko GTA0x GSM modem, which consists of the |
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12 * K5A3281 flash+RAM MCP plus the 512 KiB of internal RAM in the |
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13 * Calypso (PD751992A) chip itself. |
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14 * |
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15 * More recent revision: the present version has been concocted in order to |
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16 * squeeze TI's pdt_2092 configuration (on-board UI enabled) into the same |
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17 * small physical memory config, with the additional complication that we need |
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18 * a lot of RAM for our enlargement of RVT's memory bank which is in turn |
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19 * needed for our external LCD output hack. We will probably have to use |
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20 * this linker script version for pdt_2091 built in this tree as well, |
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21 * as it's too difficult to conditionalize the RVT enlargement on pdt_2092. |
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22 */ |
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23 |
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24 -c /* Autoinitialize variables at runtime */ |
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25 |
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26 /*********************************/ |
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27 /* SPECIFY THE SYSTEM MEMORY MAP */ |
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28 /*********************************/ |
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29 |
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30 MEMORY |
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31 { |
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32 /* CS0: Flash 4 Mbytes ****************************************************/ |
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33 /* Interrupt Vectors Table */ |
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34 I_MEM (RXI) : org = 0x00000000 len = 0x00000100 |
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35 |
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36 /* Boot Sector */ |
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37 B_MEM (RXI) : org = 0x00000100 len = 0x00001f00 |
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38 |
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39 /* Magic Word for Calypso Boot ROM */ |
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40 MWC_MEM (RXI) : org = 0x00002000 len = 0x00000004 fill = 0x0000001 |
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41 |
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42 /* Program Memory */ |
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43 P_MEM1 (RXI) : org = 0x00004000 len = 0x00000700 |
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44 P_MEM2 (RXI) : org = 0x00004700 len = 0x00000004 |
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45 P_MEM3 (RXI) : org = 0x00004704 len = 0x0037b8fc |
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46 |
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47 /* FFS Area */ |
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48 FFS_MEM (RX) : org = 0x00380000 len = 0x00080000 |
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49 /**************************************************************************/ |
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50 |
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51 /* CS1: External SRAM 1 Mbytes ********************************************/ |
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52 /* Data Memory */ |
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53 |
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54 /* |
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55 *** HACK by Spacefalcon the Outlaw *** |
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56 * |
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57 * The starting Leonardo version (gsm_ds_amd8_lj3.template) had two |
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58 * external SRAM regions: D_MEM1 and D_MEM2. When I tried removing |
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59 * D_MEM2 and keeping only D_MEM1, the linker started behaving oddly |
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60 * in that the sections were emitted in the wrong order, and the |
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61 * addresses printed in the map file were bogus. The resulting m0 |
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62 * images seemed to still work correctly, but I feel that having the |
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63 * linker act "correctly" is better. |
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64 * |
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65 * My original hack-solution was to split the 1 MiB physical XRAM |
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66 * into D_MEM1 and D_MEM2 of 512 KiB each. As it happens, the total |
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67 * XRAM usage of the standard pdt_2091 firmware is a little below |
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68 * 512 KiB anyway. |
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69 * |
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70 * Revision for pdt_2092 memory usage: D_MEM2 is now the last 64 KiB |
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71 * and D_MEM1 is the rest. |
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72 */ |
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73 |
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74 D_MEM1 (RW) : org = 0x01000000 len = 0x000F0000 |
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75 D_MEM2 (RW) : org = 0x010F0000 len = 0x00010000 |
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76 /**************************************************************************/ |
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77 |
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78 /* CS6: Calypso Internal SRAM 512 kbytes **********************************/ |
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79 /* Code & Variables Memory */ |
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80 S_MEM (RXW) : org = 0x00800000 len = 0x00080000 |
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81 /**************************************************************************/ |
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82 } |
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83 |
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84 /***********************************************/ |
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85 /* SPECIFY THE SECTIONS ALLOCATION INTO MEMORY */ |
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86 /***********************************************/ |
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87 |
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88 /* |
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89 * Since the bootloader directly calls the INT_Initialize() routine located |
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90 * in int.s, this int.s code must always be mapped at the same address |
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91 * (usually in the second flash sector). Its length is about 0x500 bytes. |
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92 * Then comes the code that need to be loaded into the internal RAM. |
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93 */ |
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94 |
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95 SECTIONS |
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96 { |
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97 .intvecs : {} > I_MEM /* Interrupt Vectors Table */ |
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98 .monitor : > B_MEM /* Monitor Constants & Code */ |
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99 { |
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100 $(CONST_BOOT_LIB) |
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101 } |
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102 |
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103 .inttext : {} > P_MEM1 /* int.s Code */ |
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104 |
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105 .bss_dar : > D_MEM1 /* DAR SWE Variables */ |
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106 { |
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107 $(BSS_DAR_LIB) |
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108 } |
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109 |
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110 /* |
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111 * The .bss section should not be split to ensure it is initialized to 0 |
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112 * each time the SW is reset. So the whole .bss is mapped either in D_MEM1 |
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113 * or in D_MEM2. |
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114 * |
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115 * Falcon's note for K5A3281: see the comments above where the memory |
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116 * regions are defined. |
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117 */ |
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118 |
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119 .bss : > D_MEM1 | D_MEM2 /* Global & Static Variables */ |
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120 { |
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121 $(BSS_BOOT_LIB) |
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122 } |
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123 |
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124 /* |
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125 * All .bss sections, which must be mapped in internal RAM must be |
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126 * grouped in order to initialized the corresponding memory to 0. |
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127 * This initialization is done in int.s file before calling the Nucleus |
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128 * routine. |
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129 */ |
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130 |
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131 GROUP |
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132 { |
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133 S_D_Mem /* Label of start address of .bss section in Int. RAM */ |
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134 .DintMem |
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135 { |
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136 |
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137 /* |
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138 * .bss sections of the application |
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139 */ |
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140 |
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141 $(BSS_LIBS) |
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142 |
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143 } |
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144 |
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145 API_HISR_stack : {} |
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146 |
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147 E_D_Mem /* Label of end address of .bss section in Int. RAM */ |
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148 } > S_MEM |
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149 |
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150 /* |
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151 * .text and .const sections which must be mapped in internal RAM. |
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152 */ |
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153 |
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154 .ldfl : {} > P_MEM2 /* Used to know the start load address */ |
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155 GROUP load = P_MEM3, run = S_MEM |
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156 { |
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157 S_P_Mem /* Label of start address of .text & .const sections in Int. RAM */ |
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158 .PIntMem |
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159 { |
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160 /* |
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161 * .text and .const sections of the application. |
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162 * |
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163 * The .veneer sections correspond exactly to .text:v&n sections |
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164 * implementing the veneer functions. The .text:v$n -> .veneer |
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165 * translation is performed by PTOOL software when PTOOL_OPTIONS |
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166 * environement variable is set to veneer_section. |
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167 */ |
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168 |
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169 $(CONST_LIBS) |
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170 |
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171 } |
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172 E_P_Mem /* Label of end address of .text and .const sections in Int. RAM */ |
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173 } |
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174 |
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175 /* |
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176 * The rest of the code is mapped in flash, however the trampolines |
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177 * load address should be consistent with .text. |
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178 */ |
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179 COMMENT2START |
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180 `trampolines load = P_MEM3, run = S_MEM |
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181 COMMENT2END |
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182 |
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183 .text : {} > P_MEM3 /* Code */ |
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184 |
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185 /* |
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186 * The rest of the constants is mapped in flash. |
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187 * The .cinit section should not be split. |
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188 */ |
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189 |
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190 .cinit : {} > P_MEM3 /* Initialization Tables */ |
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191 .const : {} > P_MEM3 /* Constant Data */ |
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192 KadaAPI : {} > P_MEM3 /* ROMized CLDC */ |
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193 |
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194 .javastack: {} >> D_MEM1 | D_MEM2 /* Java stack */ |
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195 |
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196 .stackandheap : > D_MEM1 /* System Stacks, etc... */ |
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197 { |
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198 /* Leave 20 32bit words for register pushes. */ |
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199 . = align(8); |
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200 . += 20 * 4; |
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201 |
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202 /* Stack for abort and/or undefined modes. */ |
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203 exception_stack = .; |
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204 |
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205 /* Leave 38 32bit words for state saving on exceptions. */ |
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206 _xdump_buffer = .; |
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207 . += 38 * 4; |
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208 . = align(8); |
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209 |
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210 /* Beginning of stacks and heap area - 2.75 kbytes (int.s) */ |
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211 stack_segment = .; |
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212 . += 0xB00; |
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213 } |
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214 |
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215 .data : {} > D_MEM1 /* Initialized Data */ |
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216 .sysmem : {} > D_MEM1 /* Dynamic Memory Allocation Area */ |
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217 |
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218 } |