FreeCalypso > hg > tcs211-l1-reconst
annotate chipsetsw/layer1/p_cfile/l1p_driv.c @ 317:3a2c43579200
l1p_driv.c: initial import from LoCosto source
author | Mychaela Falconia <falcon@freecalypso.org> |
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date | Wed, 04 Oct 2017 04:36:06 +0000 |
parents | 6814a6bced4f |
children | 08caa229dfa2 |
rev | line source |
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1 /************* Revision Controle System Header ************* |
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2 * GSM Layer 1 software |
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3 * L1P_DRIVE.C |
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4 * |
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5 * Filename l1p_driv.c |
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6 * Copyright 2003 (C) Texas Instruments |
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7 * |
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8 ************* Revision Controle System Header *************/ |
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9 |
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10 #define L1P_DRIVE_C |
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11 |
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12 #include "l1_macro.h" |
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13 #include "l1_confg.h" |
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14 |
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15 #if L1_GPRS |
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16 #if (CODE_VERSION == SIMULATION) |
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17 #include <string.h> |
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18 #include "l1_types.h" |
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19 #include "sys_types.h" |
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20 #include "l1_const.h" |
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21 #include "l1_time.h" |
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22 #if TESTMODE |
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23 #include "l1tm_defty.h" |
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24 #endif |
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25 #if (AUDIO_TASK == 1) |
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26 #include "l1audio_const.h" |
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27 #include "l1audio_cust.h" |
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28 #include "l1audio_defty.h" |
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29 #endif |
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30 #if (L1_GTT == 1) |
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31 #include "l1gtt_const.h" |
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32 #include "l1gtt_defty.h" |
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33 #endif |
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34 #if (L1_MP3 == 1) |
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35 #include "l1mp3_defty.h" |
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36 #endif |
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37 #if (L1_MIDI == 1) |
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38 #include "l1midi_defty.h" |
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39 #endif |
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40 #include "l1_defty.h" |
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41 #include "l1_varex.h" |
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42 #include "cust_os.h" |
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43 #include "l1_msgty.h" |
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44 #if L2_L3_SIMUL |
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45 #include "hw_debug.h" |
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46 #endif |
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47 |
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48 #include "l1p_cons.h" |
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49 #include "l1p_msgt.h" |
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50 #include "l1p_deft.h" |
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51 #include "l1p_vare.h" |
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52 #include "l1p_tabs.h" |
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53 |
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54 #include "sim_cons.h" |
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55 #include "sim_def.h" |
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56 extern T_hw FAR hw; |
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57 #include "l1_proto.h" |
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58 |
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59 #else |
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60 |
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61 #include <string.h> |
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62 #include "l1_types.h" |
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63 #include "sys_types.h" |
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64 #include "l1_const.h" |
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65 #include "l1_time.h" |
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66 |
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67 #if TESTMODE |
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68 #include "l1tm_defty.h" |
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69 #endif |
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70 #if (AUDIO_TASK == 1) |
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71 #include "l1audio_const.h" |
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72 #include "l1audio_cust.h" |
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73 #include "l1audio_defty.h" |
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74 #endif |
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75 #if (L1_GTT == 1) |
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76 #include "l1gtt_const.h" |
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77 #include "l1gtt_defty.h" |
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78 #endif |
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79 #if (L1_MP3 == 1) |
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80 #include "l1mp3_defty.h" |
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81 #endif |
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82 #if (L1_MIDI == 1) |
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83 #include "l1midi_defty.h" |
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84 #endif |
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85 #include "l1_defty.h" |
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86 #include "l1_varex.h" |
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87 #include "cust_os.h" |
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88 #include "l1_msgty.h" |
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89 #if L2_L3_SIMUL |
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90 #include "hw_debug.h" |
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91 #endif |
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92 |
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93 #include "l1p_cons.h" |
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94 #include "l1p_msgt.h" |
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95 #include "l1p_deft.h" |
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96 #include "l1p_vare.h" |
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97 #include "l1p_tabs.h" |
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98 |
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99 #include "l1_proto.h" |
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100 #include "tpudrv.h" |
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101 |
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102 #endif |
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103 |
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104 #if(RF_FAM == 61) |
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105 #include "l1_rf61.h" |
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106 #include "tpudrv61.h" |
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107 #include "l1_ctl.h" |
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108 #endif |
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109 |
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110 /*-------------------------------------------------------*/ |
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111 /* Prototypes of external functions used in this file. */ |
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112 /*-------------------------------------------------------*/ |
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113 void l1dmacro_synchro (UWORD32 when, UWORD32 value); |
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114 void l1dmacro_offset (UWORD32 offset_value, WORD32 relative_time); |
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115 void l1dmacro_afc (UWORD16 afc_value, UWORD8 win_id); |
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116 |
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117 #if ((ANLG_FAM == 1) || (ANLG_FAM == 2) || (ANLG_FAM == 3) || (RF_FAM == 61) ) |
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118 UWORD16 Cust_get_pwr_data(UWORD8 txpwr, UWORD16 radio_freq |
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119 #if(REL99 && FF_PRF) |
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120 ,UWORD8 number_uplink_timeslot |
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121 #endif |
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122 ); |
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123 #endif |
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124 void Cust_get_ramp_tab(API *a_ramp, UWORD8 txpwr_ramp_up, UWORD8 txpwr_ramp_down, UWORD16 radio_freq); |
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125 |
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126 BOOL l1ps_swap_iq_ul (UWORD16 radio_freq); |
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127 BOOL l1ps_swap_iq_dl (UWORD16 radio_freq); |
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128 #if (L1_MADC_ON == 1) |
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129 #if (RF_FAM == 61) |
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130 void l1pdmacro_rx_up (UWORD16 radio_freq,UWORD8 adc_active, UWORD8 csf_filter_choice |
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131 #if (NEW_SNR_THRESHOLD == 1) |
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132 ,UWORD8 saic_flag |
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133 #endif /* NEW_SNR_THRESHOLD == 1*/ |
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134 ); |
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135 #endif |
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136 #else /* RF_FAM == 61*/ |
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137 void l1pdmacro_rx_up (UWORD16 radio_freq, UWORD8 csf_filter_choice); |
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138 #endif |
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139 void l1pdmacro_rx_down (UWORD16 radio_freq, UWORD8 num_rx, BOOL rx_done_flag); |
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140 void l1pdmacro_tx_up (UWORD16 radio_freq); |
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141 void l1pdmacro_tx_down (UWORD16 radio_freq, WORD16 time, BOOL tx_flag, UWORD8 timing_advance,UWORD8 adc_active); |
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142 void l1pdmacro_tx_synth(UWORD16 radio_freq); |
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143 void l1pdmacro_anchor (WORD16 time); |
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144 |
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145 void l1dmacro_rx_synth(UWORD16 radio_freq); |
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146 void l1dmacro_agc(UWORD16 radio_freq, WORD8 agc_value, UWORD8 lna_off |
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147 #if (RF_FAM == 61) |
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148 ,UWORD8 if_ctl |
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149 #endif |
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150 ); |
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151 #if (CODE_VERSION == SIMULATION) |
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152 void l1dmacro_rx_ms (UWORD16 arfcn, BOOL rxnb_select); |
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153 #else |
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154 #if (L1_MADC_ON == 1) |
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155 #if (RF_FAM == 61) |
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156 void l1dmacro_rx_ms (UWORD16 arfcn,UWORD8 adc_active); |
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157 #endif |
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158 #else |
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159 void l1dmacro_rx_ms (UWORD16 arfcn); |
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160 #endif |
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161 #endif |
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162 void l1pdmacro_it_dsp_gen(WORD16 time); |
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163 |
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164 /*-------------------------------------------------------*/ |
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165 /* Prototypes of functions defined in this file. */ |
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166 /*-------------------------------------------------------*/ |
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167 // TPU Drivers... |
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168 |
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169 |
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170 // DSP Drivers... |
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171 void l1pddsp_synchro (UWORD8 switch_mode, UWORD8 camp_timeslot); |
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172 void l1pddsp_idle_prach_data (BOOL polling, UWORD8 cs_type, UWORD16 channel_request_data, |
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173 UWORD8 bsic, UWORD16 radio_freq); |
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174 void l1pddsp_idle_prach_power (UWORD8 txpwr, UWORD16 radio_freq, UWORD8 ts); |
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175 void l1pddsp_single_tx_block (UWORD8 burst_nb, UWORD8 *data, UWORD8 tsc, |
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176 UWORD16 radio_freq); |
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177 #if FF_L1_IT_DSP_USF |
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178 void l1pddsp_idle_rx_nb (UWORD8 burst_nb, UWORD8 tsq, UWORD16 radio_freq, |
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179 UWORD8 timeslot_no, BOOL ptcch_dl, BOOL usf_interrupt); |
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180 #else |
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181 void l1pddsp_idle_rx_nb (UWORD8 burst_nb, UWORD8 tsq, UWORD16 radio_freq, |
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182 UWORD8 timeslot_no, BOOL ptcch_dl); |
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183 #endif |
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184 void l1pddsp_transfer_mslot_ctrl (UWORD8 burst_nb, UWORD8 dl_bitmap, UWORD8 ul_bitmap, |
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185 UWORD8 *usf_table, UWORD8 mac_mode, UWORD8 *ul_buffer_index, |
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186 UWORD8 tsc, UWORD16 radio_freq, UWORD8 synchro_timeslot, |
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187 #if FF_L1_IT_DSP_USF |
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188 UWORD8 dsp_usf_interrupt |
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189 #else |
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190 UWORD8 usf_vote_enable |
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191 #endif |
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192 ); |
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193 void l1pddsp_transfer_mslot_power (UWORD8 *txpwr, UWORD16 radio_freq, UWORD8 ul_bitmap); |
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194 void l1pddsp_ul_ptcch_data (UWORD8 cs_type, UWORD16 channel_request_data, UWORD8 bsic, |
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195 UWORD16 radio_freq, UWORD8 timeslot_no); |
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196 void l1pddsp_interf_meas_ctrl (UWORD8 nb_meas_req); |
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197 void l1pddsp_transfer_meas_ctrl (UWORD8 meas_position); |
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198 |
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199 /*-------------------------------------------------------*/ |
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200 /* l1pd_afc() */ |
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201 /*-------------------------------------------------------*/ |
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202 /* Parameters : */ |
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203 /* Return : */ |
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204 /* Functionality : */ |
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205 /*-------------------------------------------------------*/ |
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206 void l1pd_afc(void) |
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207 { |
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208 #if ((ANLG_FAM == 1) || (ANLG_FAM == 2) || (ANLG_FAM == 3)) |
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209 l1ddsp_load_afc(l1s.afc); |
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210 #endif |
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211 #if (RF_FAM == 61) |
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212 l1dtpu_load_afc(l1s.afc); |
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213 #endif |
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214 } |
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215 |
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216 /*-------------------------------------------------------*/ |
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217 /* l1pdtpu_interf_meas() */ |
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218 /*-------------------------------------------------------*/ |
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219 /* Parameters : */ |
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220 /* Return : */ |
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221 /* Functionality : */ |
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222 /*-------------------------------------------------------*/ |
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223 UWORD8 l1pdtpu_interf_meas(UWORD16 radio_freq, |
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224 WORD8 agc, |
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225 UWORD8 lna_off, |
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226 UWORD8 meas_bitmap, |
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227 UWORD32 offset_serv, |
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228 UWORD16 win_id, |
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229 UWORD8 synchro_ts |
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230 #if (RF_FAM == 61) |
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231 ,UWORD8 if_ctl |
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232 #endif |
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233 ) |
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234 { |
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235 UWORD8 bit_mask = 0x80; |
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236 UWORD8 ts; |
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237 BOOL rf_programmed = FALSE; |
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238 UWORD8 count = 0; |
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239 |
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240 if(!win_id) |
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241 { |
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242 // Nothing programmed yet, we must avoid Mirror effect in Ctrl phase. |
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243 l1pdmacro_anchor(l1_config.params.rx_change_offset_time); |
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244 } |
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245 |
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246 for (ts=0; ts<8; ts++) |
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247 { |
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248 // the bitmap corresponds to that of the idle frame of the network!!! |
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249 #if ((CHIPSET==3)||(CHIPSET == 4)) |
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250 // limitation of 5 measurements for SAMSON (TPU RAM size limitation) |
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251 if((meas_bitmap & bit_mask)&&(count <= 4)) |
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252 #else |
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253 if(meas_bitmap & bit_mask) |
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254 #endif |
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255 { |
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256 UWORD16 local_win_id; |
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257 UWORD16 offset; |
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258 WORD16 when; |
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259 UWORD16 offset_chg; |
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260 |
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261 if((ts>synchro_ts) && (count==0)) |
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262 { |
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263 // The 1st Work does not contain any Interf meas. |
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264 // We must ovoid a possible Mirror effect for the rest of TS. |
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265 l1pdmacro_anchor(l1_config.params.rx_change_offset_time); |
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266 } |
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267 |
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268 // Increment nbr of meas. programmed. |
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269 count++; |
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270 |
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271 local_win_id = (8 - synchro_ts + ts) * BP_SPLIT; |
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272 if(local_win_id >= (BP_SPLIT * 8)) local_win_id -= BP_SPLIT * 8; // Modulo. |
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273 |
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274 // Compute offset |
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275 offset_chg = ((local_win_id * BP_DURATION) >> BP_SPLIT_PW2); |
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276 offset = offset_serv + offset_chg; |
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277 if(offset >= TPU_CLOCK_RANGE) offset -= TPU_CLOCK_RANGE; |
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278 |
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279 if(!rf_programmed) |
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280 { |
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281 // Compute offset change timing |
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282 when = offset_chg + |
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283 PROVISION_TIME - |
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284 l1_config.params.rx_synth_setup_time - |
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285 EPSILON_OFFS; |
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286 |
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287 if(when < 0) when += TPU_CLOCK_RANGE; |
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288 |
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289 // Program TPU scenario |
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290 l1dmacro_offset (offset, when); // change TPU offset according to win_id |
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291 l1dmacro_rx_synth (radio_freq); // pgme SYNTH. |
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292 #if (RF_FAM !=61) |
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293 l1dmacro_agc (radio_freq, agc,lna_off); // pgme AGC. |
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294 #endif |
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295 |
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296 #if (RF_FAM == 61) |
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297 l1dmacro_agc (radio_freq, agc,lna_off, if_ctl); // pgme AGC. |
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298 #endif |
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299 |
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300 rf_programmed = TRUE; |
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301 } |
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302 else |
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303 { |
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304 // Compute offset change timing |
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305 when = offset_chg - BP_DURATION + PROVISION_TIME + PW_ACQUIS_DURATION + 20; |
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306 if(when < 0) when += TPU_CLOCK_RANGE; |
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307 |
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308 // Program TPU scenario |
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309 l1dmacro_offset (offset, when); // change TPU offset according to win_id |
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310 } |
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311 |
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312 #if (CODE_VERSION == SIMULATION) |
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313 l1dmacro_rx_ms (radio_freq, 1); // pgm PWR acquisition. |
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314 #else |
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315 #if (L1_MADC_ON == 1) |
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316 #if (RF_FAM == 61) |
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317 l1dmacro_rx_ms (radio_freq,INACTIVE); // pgm PWR acquisition. |
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318 #endif |
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319 #else |
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320 l1dmacro_rx_ms (radio_freq); // pgm PWR acquisition. |
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321 #endif |
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322 #endif |
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323 |
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324 l1dmacro_offset (offset_serv, IMM); // restore offset |
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325 } |
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326 |
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327 bit_mask >>= 1; |
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328 |
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329 } // for(ts... |
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330 |
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331 return(count); |
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332 } |
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333 |
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334 /*-------------------------------------------------------*/ |
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335 /* l1dtpu_serv_rx() */ |
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336 /*-------------------------------------------------------*/ |
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337 /* Parameters : */ |
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338 /* rx_id: range 0-7, first slot of RX group */ |
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339 /* rx_group_id: used in case |RX| |RX| */ |
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340 /* */ |
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341 /* Return : */ |
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342 /* Functionality : */ |
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343 /*-------------------------------------------------------*/ |
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344 void l1pdtpu_serv_rx_nb(UWORD16 radio_freq, WORD8 agc, UWORD8 lna_off, |
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345 UWORD8 rx_id, UWORD32 offset_serv, UWORD8 num_rx, |
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346 UWORD8 rx_group_id, BOOL rx_done_flag,UWORD8 adc_active, |
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347 UWORD8 csf_filter_choice |
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348 #if (RF_FAM == 61) |
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349 ,UWORD8 if_ctl |
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350 #endif |
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351 #if (NEW_SNR_THRESHOLD == 1) |
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352 ,UWORD8 saic_flag |
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353 #endif /* NEW_SNR_THRESHOLD*/ |
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354 ) |
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355 { |
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356 UWORD16 offset; |
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357 |
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358 #if (CODE_VERSION == SIMULATION) |
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359 UWORD32 tpu_w_page; |
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360 |
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361 if (hw.tpu_r_page==0) |
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362 tpu_w_page=1; |
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363 else |
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364 tpu_w_page=0; |
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365 |
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366 hw.rx_id[tpu_w_page][rx_group_id-1]=rx_id; |
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367 hw.num_rx[tpu_w_page][rx_group_id-1]=num_rx; |
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368 hw.rx_group_id[tpu_w_page]=rx_group_id; |
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369 #endif |
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370 |
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371 offset = offset_serv + (rx_id * BP_DURATION); |
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372 if(offset >= TPU_CLOCK_RANGE) offset -= TPU_CLOCK_RANGE; |
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373 |
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374 if (rx_group_id == 1) |
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375 { |
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376 // Time tracking. |
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377 l1dmacro_synchro (l1_config.params.rx_change_synchro_time, offset_serv); // Adjust serving OFFSET. |
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378 |
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379 #if L2_L3_SIMUL |
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380 #if (DEBUG_TRACE == BUFFER_TRACE_OFFSET) |
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381 buffer_trace(3, 0x43, offset_serv, l1s.actual_time.fn, 0); |
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382 #endif |
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383 #endif |
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384 |
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385 // Change offset to align on RX. |
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386 l1dmacro_offset(offset, IMM); |
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387 |
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388 // Program Synth. |
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389 // Program ADC measurement |
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390 // Program AGC. |
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391 l1dmacro_rx_synth(radio_freq); |
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392 if(adc_active == ACTIVE) |
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393 l1dmacro_adc_read_rx(); |
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394 |
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395 l1dmacro_agc (radio_freq, agc, lna_off |
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396 #if (RF_FAM == 61) |
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397 ,if_ctl |
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398 #endif |
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399 ); |
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400 } |
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401 else |
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402 { |
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403 // Change offset to align on RX. |
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404 l1dmacro_offset(offset, IMM); // Change offset to align on RX. |
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405 } |
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406 |
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407 l1pdmacro_rx_up (radio_freq,adc_active, csf_filter_choice |
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408 #if (NEW_SNR_THRESHOLD == 1) |
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409 ,saic_flag |
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410 #endif /* NEW_SNR_THRESHOLD*/ |
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411 |
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412 ); // RX window opened. |
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413 l1pdmacro_rx_down(radio_freq, num_rx, rx_done_flag); // RX window closed. |
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414 |
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415 // Restore offset to synchro value. |
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416 l1dmacro_offset (offset_serv, IMM); |
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417 } |
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418 |
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419 /*-------------------------------------------------------*/ |
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420 /* l1dtpu_serv_tx() */ |
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421 /*-------------------------------------------------------*/ |
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422 /* Parameters : */ |
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423 /* Return : */ |
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424 /* Functionality : */ |
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425 /*-------------------------------------------------------*/ |
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426 #if ((ANLG_FAM == 1) || (ANLG_FAM == 2) || (ANLG_FAM == 3)) |
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427 #ifndef ABB_RAMP_UP_TIME //Flexi ABB Delays defines it in tpudrvXX.h |
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428 #define ABB_RAMP_UP_TIME 32 // maximum time for ramp up |
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429 #endif |
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430 |
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431 #ifndef ABB_RAMP_DELAY//Flexi ABB Delays defines it in tpudrvXX.h |
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432 #define ABB_RAMP_DELAY 6 // minimum ramp delay APCDEL |
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433 #endif |
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434 |
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435 #ifndef ABB_BULON_HOLD_TIME //Flexi ABB Delays defines it in tpudrvXX.h |
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436 #define ABB_BULON_HOLD_TIME 32 // min. hold time for BULON after BULENA down |
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437 #endif |
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438 |
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439 |
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440 #endif |
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441 void l1pdtpu_serv_tx(UWORD16 radio_freq, |
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442 UWORD8 timing_advance, |
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443 UWORD32 offset_serv, |
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444 UWORD8 tx_id, |
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445 UWORD8 num_tx, |
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446 UWORD8 tx_group_id, |
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447 UWORD8 switch_flag, |
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448 BOOL burst_type, |
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449 BOOL rx_flag, |
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450 UWORD8 adc_active) |
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451 { |
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452 WORD16 time; |
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453 UWORD32 offset_tx; |
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454 UWORD32 timing_advance_in_qbit = (UWORD32)timing_advance << 2; |
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455 #if ((ANLG_FAM == 1) || (ANLG_FAM == 2) || (ANLG_FAM == 3) || (RF_FAM == 61)) |
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456 UWORD16 apcdel1_data, apcdel1_data_up; |
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457 #endif |
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458 UWORD8 i; |
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459 static UWORD8 static_switch_flag = 0; |
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|
460 |
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461 #if (CODE_VERSION == SIMULATION) |
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462 UWORD32 tpu_w_page; |
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|
463 |
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464 if (hw.tpu_r_page==0) |
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465 tpu_w_page=1; |
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466 else |
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467 tpu_w_page=0; |
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|
468 |
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469 hw.tx_id[tpu_w_page][tx_group_id-1]=tx_id; |
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470 hw.num_tx[tpu_w_page][tx_group_id-1]=num_tx; |
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471 hw.tx_group_id[tpu_w_page]=tx_group_id; |
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|
472 #endif |
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|
473 |
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474 // Reset timing advance if TA_ALGO not enabled. |
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475 #if !TA_ALGO |
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476 timing_advance_in_qbit = 0; |
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477 #endif |
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|
478 |
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479 // In case another group of TX bursts is called, the previous slot was a hole |
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480 // An IT has to be generated to the DSP so that ramps and power level are reloaded |
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481 // This does not apply to combinations of PRACH and TX NB |
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482 if ((tx_group_id > 1) && (!static_switch_flag)) |
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|
483 { |
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|
484 // exact timing for generation of IT during hole not required but |
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485 // time > time of previous ramp down (BULENA -> BULON down = 32 qb) + margin (10 qb) |
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486 #if (RF_FAM != 61) |
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487 time = TX_TABLE[tx_id-1] + PROVISION_TIME + ABB_BULON_HOLD_TIME + 10 |
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488 - l1_config.params.prg_tx_gsm; |
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489 #endif |
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|
490 |
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491 #if (RF_FAM == 61) |
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|
492 time = TX_TABLE[tx_id-1] + PROVISION_TIME + APC_RAMP_DOWN_TIME + 10 |
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493 - l1_config.params.prg_tx_gsm; |
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494 #endif |
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|
495 |
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|
496 if (burst_type == TX_NB_BURST) |
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497 time -= timing_advance_in_qbit; // time can never be negative here |
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changeset
|
498 |
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|
499 l1pdmacro_it_dsp_gen(time); |
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|
500 } |
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changeset
|
501 |
3a2c43579200
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changeset
|
502 |
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changeset
|
503 if (tx_group_id == 1) |
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|
504 { |
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|
505 #if ((ANLG_FAM == 1) || (ANLG_FAM == 2) || (ANLG_FAM == 3)) |
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diff
changeset
|
506 //MS TX, set ABB in MS mode |
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|
507 #if (DSP == 33) || (DSP == 34) || (DSP == 35) || (DSP == 36) || (DSP == 37) |
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|
508 // ABB set to MS mode if |TX|TX|.., |TX|PRACH|, |PRACH|TX| or |PRACH|PRACH| |
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|
509 // switch_flag is set for the first burst of TX/PRACH or PRACH/PRACH combinations |
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|
510 // MS mode in ABB must be maintained for second burst (static_switch_flag) |
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|
511 if ((num_tx > 1) || (switch_flag) || (static_switch_flag)) |
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|
512 l1ps_dsp_com.pdsp_ndb_ptr->d_bbctrl_gprs = l1_config.params.bbctrl | B_MSLOT; |
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|
513 else |
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|
514 l1ps_dsp_com.pdsp_ndb_ptr->d_bbctrl_gprs = l1_config.params.bbctrl; |
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|
515 #endif |
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|
516 #endif |
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|
517 } |
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|
518 else |
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|
519 { |
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|
520 // handle special case |TX| |TX|TX| |
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|
521 #if ((ANLG_FAM == 1) || (ANLG_FAM == 2) || (ANLG_FAM == 3)) |
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|
522 //MS TX, set ABB in MS mode |
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523 #if (DSP == 33) || (DSP == 34) || (DSP == 35) || (DSP == 36) || (DSP == 37) |
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|
524 if ((num_tx > 1) || (switch_flag) || (static_switch_flag)) |
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|
525 l1ps_dsp_com.pdsp_ndb_ptr->d_bbctrl_gprs = l1_config.params.bbctrl | B_MSLOT; |
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526 #endif |
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527 #endif |
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|
528 } |
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|
529 |
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530 // Compute offset value for TX. |
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|
531 // PRG_TX has become variable, no longer contained in TIME_OFFSET_TX ! |
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|
532 if ((burst_type == TX_NB_BURST) || (switch_flag==1)) |
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|
533 { |
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|
534 offset_tx = offset_serv + TX_TABLE[tx_id] + PROVISION_TIME |
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|
535 - l1_config.params.prg_tx_gsm - timing_advance_in_qbit; |
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|
536 } |
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|
537 else |
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538 { |
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539 offset_tx = offset_serv + TX_TABLE[tx_id] + PROVISION_TIME |
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|
540 - l1_config.params.prg_tx_gsm; |
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|
541 } |
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|
542 |
3a2c43579200
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|
543 // offset_tx mod 5000 |
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changeset
|
544 if (offset_tx >= TPU_CLOCK_RANGE) |
3a2c43579200
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changeset
|
545 offset_tx -= TPU_CLOCK_RANGE; |
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|
546 |
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|
547 if(rx_flag == TRUE) |
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548 { |
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549 time = offset_tx - |
3a2c43579200
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diff
changeset
|
550 l1_config.params.tx_synth_setup_time - |
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parents:
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diff
changeset
|
551 EPSILON_OFFS |
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|
552 - offset_serv; |
3a2c43579200
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|
553 if ((burst_type == TX_NB_BURST) || (switch_flag==1)) |
3a2c43579200
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554 time += timing_advance_in_qbit - TA_MAX; |
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|
555 } |
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556 else |
3a2c43579200
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557 time = TPU_CLOCK_RANGE - EPSILON_SYNC; |
3a2c43579200
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parents:
15
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changeset
|
558 |
3a2c43579200
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559 if (time < 0) |
3a2c43579200
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changeset
|
560 time += TPU_CLOCK_RANGE; |
3a2c43579200
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changeset
|
561 |
3a2c43579200
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diff
changeset
|
562 if (!static_switch_flag) |
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diff
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|
563 l1dmacro_offset (offset_tx, (WORD32) time); // load OFFSET for TX before each burst. |
3a2c43579200
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diff
changeset
|
564 |
3a2c43579200
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diff
changeset
|
565 #if L2_L3_SIMUL |
3a2c43579200
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diff
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|
566 #if (DEBUG_TRACE == BUFFER_TRACE_OFFSET) |
3a2c43579200
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|
567 buffer_trace(2, offset_tx,l1s.actual_time.fn,0,0); |
3a2c43579200
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diff
changeset
|
568 #endif |
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diff
changeset
|
569 #endif |
3a2c43579200
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Mychaela Falconia <falcon@freecalypso.org>
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15
diff
changeset
|
570 |
3a2c43579200
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diff
changeset
|
571 time=0; |
3a2c43579200
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diff
changeset
|
572 |
3a2c43579200
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Mychaela Falconia <falcon@freecalypso.org>
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15
diff
changeset
|
573 // program PLL only if no TX control carried out in same frame: |TX| |TX|TX| possible |
3a2c43579200
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changeset
|
574 // |PRACH|TX|, |TX|PRACH| or |PRACH|PRACH| also possible |
3a2c43579200
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diff
changeset
|
575 if (tx_group_id == 1) |
3a2c43579200
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diff
changeset
|
576 { |
3a2c43579200
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15
diff
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|
577 l1pdmacro_tx_synth(radio_freq); // load SYNTH. |
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|
578 } |
3a2c43579200
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diff
changeset
|
579 |
3a2c43579200
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15
diff
changeset
|
580 if (!static_switch_flag) // window opened for previous time slot (TX/PRACH or PRACH/PRACH) |
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changeset
|
581 l1pdmacro_tx_up(radio_freq); // TX window opened |
3a2c43579200
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15
diff
changeset
|
582 |
3a2c43579200
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15
diff
changeset
|
583 |
3a2c43579200
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15
diff
changeset
|
584 #if (CODE_VERSION == SIMULATION) |
3a2c43579200
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Mychaela Falconia <falcon@freecalypso.org>
parents:
15
diff
changeset
|
585 if (burst_type == TX_RA_BURST) |
3a2c43579200
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parents:
15
diff
changeset
|
586 { |
3a2c43579200
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15
diff
changeset
|
587 time += l1_config.params.tx_ra_duration; |
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parents:
15
diff
changeset
|
588 } |
3a2c43579200
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parents:
15
diff
changeset
|
589 else |
3a2c43579200
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parents:
15
diff
changeset
|
590 { |
3a2c43579200
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parents:
15
diff
changeset
|
591 if (num_tx > 1) |
3a2c43579200
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parents:
15
diff
changeset
|
592 // num_tx * BP_DURATION |
3a2c43579200
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parents:
15
diff
changeset
|
593 time += TX_TABLE[num_tx - 1] + l1_config.params.tx_nb_duration; |
3a2c43579200
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parents:
15
diff
changeset
|
594 else |
3a2c43579200
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parents:
15
diff
changeset
|
595 time += l1_config.params.tx_nb_duration; |
3a2c43579200
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parents:
15
diff
changeset
|
596 } |
3a2c43579200
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diff
changeset
|
597 #else |
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15
diff
changeset
|
598 #if ((ANLG_FAM == 1) || (ANLG_FAM == 2) || (ANLG_FAM == 3)) |
3a2c43579200
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parents:
15
diff
changeset
|
599 // Read APCDEL1 register DELU(4:0): delay of ramp up start, DELD (9:5) delay of ramp down start |
3a2c43579200
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Mychaela Falconia <falcon@freecalypso.org>
parents:
15
diff
changeset
|
600 // This value is used for computations in MS TX or TX/PRACH combinations |
3a2c43579200
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Mychaela Falconia <falcon@freecalypso.org>
parents:
15
diff
changeset
|
601 // This value is not modified by the computations |
3a2c43579200
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Mychaela Falconia <falcon@freecalypso.org>
parents:
15
diff
changeset
|
602 apcdel1_data = (l1s_dsp_com.dsp_ndb_ptr->d_apcdel1 >> 6) & 0x03ff; |
3a2c43579200
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parents:
15
diff
changeset
|
603 apcdel1_data_up = apcdel1_data & 0x001f; //delay of ramp up start |
3a2c43579200
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parents:
15
diff
changeset
|
604 #endif |
3a2c43579200
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parents:
15
diff
changeset
|
605 |
3a2c43579200
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parents:
15
diff
changeset
|
606 #if (RF_FAM == 61) |
3a2c43579200
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Mychaela Falconia <falcon@freecalypso.org>
parents:
15
diff
changeset
|
607 // Read APCDEL1 register DELU(4:0): delay of ramp up start, DELD (9:5) delay of ramp down start |
3a2c43579200
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15
diff
changeset
|
608 // This value is used for computations in MS TX or TX/PRACH combinations |
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15
diff
changeset
|
609 // This value is not modified by the computations |
3a2c43579200
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diff
changeset
|
610 apcdel1_data = (l1s_dsp_com.dsp_ndb_ptr->d_apcdel1) & 0x03ff; |
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diff
changeset
|
611 apcdel1_data_up = apcdel1_data & 0x001f; //delay of ramp up start |
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15
diff
changeset
|
612 #endif |
3a2c43579200
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15
diff
changeset
|
613 |
3a2c43579200
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15
diff
changeset
|
614 if (!switch_flag) |
3a2c43579200
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diff
changeset
|
615 { |
3a2c43579200
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diff
changeset
|
616 if (burst_type == TX_NB_BURST) |
3a2c43579200
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diff
changeset
|
617 { |
3a2c43579200
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diff
changeset
|
618 // If PRACH precedes TX normal burst(s) we have to add BP_DURATION |
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diff
changeset
|
619 if (static_switch_flag) |
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changeset
|
620 time += BP_DURATION; |
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diff
changeset
|
621 |
3a2c43579200
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diff
changeset
|
622 // generate DSP IT for each TX slot after ramp up |
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|
623 // Margin: |
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diff
changeset
|
624 // ABB_RAMP_DELAY = 4*1.5bits internal ABB delay BULENA ON -> ramp up |
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diff
changeset
|
625 // apcdel1_data_up = additional delay BULENA ON -> ramp up |
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diff
changeset
|
626 // ABB_RAMP_UP_TIME: maximum time for ramp up: 16 coeff. |
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diff
changeset
|
627 // 10 qbits of additional margin |
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diff
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|
628 #if ((ANLG_FAM == 1) || (ANLG_FAM == 2) || (ANLG_FAM == 3)) |
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changeset
|
629 for (i=0; i<num_tx; i++) |
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|
630 l1pdmacro_it_dsp_gen(time + ABB_RAMP_DELAY + ABB_RAMP_UP_TIME + i*BP_DURATION + apcdel1_data_up + 10); |
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changeset
|
631 #endif |
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15
diff
changeset
|
632 |
3a2c43579200
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changeset
|
633 #if (RF_FAM == 61) |
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15
diff
changeset
|
634 for (i=0; i<num_tx; i++) |
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diff
changeset
|
635 l1pdmacro_it_dsp_gen(time + APC_RAMP_DELAY + APC_RAMP_UP_TIME + i*BP_DURATION + apcdel1_data_up + 10); |
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|
636 #endif |
3a2c43579200
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diff
changeset
|
637 |
3a2c43579200
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diff
changeset
|
638 |
3a2c43579200
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diff
changeset
|
639 if (num_tx > 1) |
3a2c43579200
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15
diff
changeset
|
640 // (num_tx - 1) * BP_DURATION + normal burst duration |
3a2c43579200
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diff
changeset
|
641 time += TX_TABLE[num_tx - 1] + l1_config.params.tx_nb_duration - (num_tx - 1); |
3a2c43579200
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|
642 else |
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643 time += l1_config.params.tx_nb_duration; |
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644 } |
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645 else //PRACH |
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646 { |
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647 // If TX NB precedes PRACH we have to add BP_DURATION and TA (in qbits) |
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648 if (static_switch_flag == 1) |
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649 { |
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650 if (timing_advance_in_qbit > 240) // clip TA, cf. comment below |
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651 timing_advance_in_qbit = 240; |
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652 time += BP_DURATION + timing_advance_in_qbit; |
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653 } |
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654 // If PRACH precedes PRACH we have to add BP_DURATION |
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655 else if (static_switch_flag == 2) |
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656 time += BP_DURATION ; |
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657 |
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658 #if ((ANLG_FAM == 1) || (ANLG_FAM == 2) || (ANLG_FAM == 3)) |
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659 l1pdmacro_it_dsp_gen(time + ABB_RAMP_DELAY + ABB_RAMP_UP_TIME + apcdel1_data_up + 10); |
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660 #endif |
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661 |
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662 #if (RF_FAM == 61) |
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663 l1pdmacro_it_dsp_gen(time + APC_RAMP_DELAY + APC_RAMP_UP_TIME + apcdel1_data_up + 10); |
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664 #endif |
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665 |
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666 time += l1_config.params.tx_ra_duration; |
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667 } |
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668 |
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669 } |
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670 else if (switch_flag == 1) // |TX|PRACH| or |PRACH|TX| |
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671 { |
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672 #if (DSP == 33) || (DSP == 34) || (DSP == 35) || (DSP == 36) || (DSP == 37) || (DSP == 38) || (DSP == 39) |
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673 // => ABB windows are opened as for TX_NB in MS mode |
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674 // => Ramp up start of PRACH is delayed inside this window by the TA of the TX_NB |
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675 // => DSP inserts dummy bits such that ramp and modulation match |
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676 // Rem.: the TA passed for the PRACH is the one for the following TX_NB!!! |
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677 #if ((ANLG_FAM == 1) || (ANLG_FAM == 2) || (ANLG_FAM == 3)) || (RF_FAM == 61) |
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678 // In combinations of TX_NB and PRACH apcdel1_bis and apcdel2_bis apply to the PRACH |
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679 UWORD16 apcdel1_bis_data, apcdel1_bis_data_up, apcdel2_bis_data_up, prach_delay; |
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680 API d_ctrl_abb_gprs; |
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681 |
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682 // clip TA (in qbit): max. TA supported = BP_DURATION - PRACH duration - max. ramp time |
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683 // = 625 - 88*4 - 32 = 241 |
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684 if (timing_advance_in_qbit > 240) |
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685 timing_advance_in_qbit = 240; |
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686 |
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687 prach_delay = apcdel1_data_up + timing_advance_in_qbit; |
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688 apcdel1_bis_data_up = prach_delay & 0x001f; |
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689 apcdel2_bis_data_up = (prach_delay >> 5) & 0x001f; |
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690 |
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691 // For ramp down delay we need to keep the original value from APCDEL1 (bits 9:5) |
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692 // APCDEL2 default value is '0' |
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693 apcdel1_bis_data = apcdel1_bis_data_up | (apcdel1_data & 0x03e0); |
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694 |
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695 #if(RF_FAM != 61) |
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696 l1s_dsp_com.dsp_ndb_ptr->d_apcdel1_bis = (apcdel1_bis_data << 6) | 0x04; |
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697 l1s_dsp_com.dsp_ndb_ptr->d_apcdel2_bis = (apcdel2_bis_data_up << 6) | 0x34; |
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698 #else |
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699 l1s_dsp_com.dsp_ndb_ptr->d_apcdel1_bis = (apcdel1_bis_data ); |
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700 l1s_dsp_com.dsp_ndb_ptr->d_apcdel2_bis = (apcdel2_bis_data_up); |
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701 #endif |
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702 |
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703 if (burst_type == TX_RA_BURST) // |PRACH|TX| |
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704 { |
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705 |
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706 #if(RF_FAM != 61) |
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707 l1pdmacro_it_dsp_gen(time + ABB_RAMP_DELAY + ABB_RAMP_UP_TIME + prach_delay + 10); |
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708 #else |
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709 l1pdmacro_it_dsp_gen(time + APC_RAMP_DELAY + APC_RAMP_UP_TIME + prach_delay + 10); |
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710 #endif |
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711 // apcdel1_bis, apcdel2_bis must be programmed for the current ts (PRACH) |
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712 // here we need to overwrite (mask) bits for APCDEL1, APCDEL2 programming done in l1pddsp_transfer_mslot_power() |
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713 d_ctrl_abb_gprs = l1ps_dsp_com.pdsp_db_w_ptr->a_ctrl_abb_gprs[tx_id]; |
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714 d_ctrl_abb_gprs |= ((1 << B_BULRAMPDEL_BIS) | (1 << B_BULRAMPDEL2_BIS)); |
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715 d_ctrl_abb_gprs &= ~((1 << B_BULRAMPDEL) | (1 << B_BULRAMPDEL2)); |
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716 l1ps_dsp_com.pdsp_db_w_ptr->a_ctrl_abb_gprs[tx_id] = d_ctrl_abb_gprs; |
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717 } |
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718 else // |TX|PRACH| |
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719 { |
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720 #if(RF_FAM != 61) |
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721 l1pdmacro_it_dsp_gen(time + ABB_RAMP_DELAY + ABB_RAMP_UP_TIME + apcdel1_data_up + 10); |
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722 #else |
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723 l1pdmacro_it_dsp_gen(time + APC_RAMP_DELAY + APC_RAMP_UP_TIME + apcdel1_data_up + 10); |
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724 #endif |
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725 |
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726 // apcdel1_bis, apcdel2_bis must be programmed for the next ts (PRACH) |
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727 d_ctrl_abb_gprs = l1ps_dsp_com.pdsp_db_w_ptr->a_ctrl_abb_gprs[tx_id + 1]; |
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728 d_ctrl_abb_gprs |= ((1 << B_BULRAMPDEL_BIS) | (1 << B_BULRAMPDEL2_BIS)); |
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729 d_ctrl_abb_gprs &= ~((1 << B_BULRAMPDEL) | (1 << B_BULRAMPDEL2)); |
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730 l1ps_dsp_com.pdsp_db_w_ptr->a_ctrl_abb_gprs[tx_id + 1] = d_ctrl_abb_gprs; |
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731 } |
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732 #endif // ANALOG |
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733 |
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734 static_switch_flag = 1; |
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|
735 |
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736 #endif // DSP == 33 || DSP == 34 || (DSP == 36) || (DSP == 37) |
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737 } |
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738 else if (switch_flag == 2) // |PRACH|PRACH| |
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739 // Combination handled by programming ABB with MS mode = 1 |
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740 // => first burst length of first PRACH = BP_DURATION |
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741 { |
3a2c43579200
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Mychaela Falconia <falcon@freecalypso.org>
parents:
15
diff
changeset
|
742 #if ((ANLG_FAM == 1) || (ANLG_FAM == 2) || (ANLG_FAM == 3)) |
3a2c43579200
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Mychaela Falconia <falcon@freecalypso.org>
parents:
15
diff
changeset
|
743 l1pdmacro_it_dsp_gen(time + ABB_RAMP_DELAY + ABB_RAMP_UP_TIME + apcdel1_data_up + 10); |
3a2c43579200
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Mychaela Falconia <falcon@freecalypso.org>
parents:
15
diff
changeset
|
744 #endif |
3a2c43579200
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Mychaela Falconia <falcon@freecalypso.org>
parents:
15
diff
changeset
|
745 |
3a2c43579200
l1p_driv.c: initial import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
15
diff
changeset
|
746 #if (RF_FAM == 61) |
3a2c43579200
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Mychaela Falconia <falcon@freecalypso.org>
parents:
15
diff
changeset
|
747 l1pdmacro_it_dsp_gen(time + APC_RAMP_DELAY + APC_RAMP_UP_TIME + apcdel1_data_up + 10); |
3a2c43579200
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Mychaela Falconia <falcon@freecalypso.org>
parents:
15
diff
changeset
|
748 #endif |
3a2c43579200
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Mychaela Falconia <falcon@freecalypso.org>
parents:
15
diff
changeset
|
749 |
3a2c43579200
l1p_driv.c: initial import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
15
diff
changeset
|
750 static_switch_flag = 2; |
3a2c43579200
l1p_driv.c: initial import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
15
diff
changeset
|
751 } |
3a2c43579200
l1p_driv.c: initial import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
15
diff
changeset
|
752 #endif //Codeversion |
3a2c43579200
l1p_driv.c: initial import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
15
diff
changeset
|
753 |
3a2c43579200
l1p_driv.c: initial import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
15
diff
changeset
|
754 // In case of combinations TX_NB/PRACH or PRACH/PRACH the TX window is kept open |
3a2c43579200
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Mychaela Falconia <falcon@freecalypso.org>
parents:
15
diff
changeset
|
755 if (!switch_flag) |
3a2c43579200
l1p_driv.c: initial import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
15
diff
changeset
|
756 { |
3a2c43579200
l1p_driv.c: initial import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
15
diff
changeset
|
757 l1pdmacro_tx_down(radio_freq, time, switch_flag, timing_advance_in_qbit,adc_active); // TX window closed |
3a2c43579200
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Mychaela Falconia <falcon@freecalypso.org>
parents:
15
diff
changeset
|
758 |
3a2c43579200
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Mychaela Falconia <falcon@freecalypso.org>
parents:
15
diff
changeset
|
759 l1dmacro_offset (offset_serv, IMM); // Restore offset with serving value. |
3a2c43579200
l1p_driv.c: initial import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
15
diff
changeset
|
760 |
3a2c43579200
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Mychaela Falconia <falcon@freecalypso.org>
parents:
15
diff
changeset
|
761 static_switch_flag = 0; |
3a2c43579200
l1p_driv.c: initial import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
15
diff
changeset
|
762 } |
3a2c43579200
l1p_driv.c: initial import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
15
diff
changeset
|
763 |
3a2c43579200
l1p_driv.c: initial import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
15
diff
changeset
|
764 #if L2_L3_SIMUL |
3a2c43579200
l1p_driv.c: initial import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
15
diff
changeset
|
765 #if (DEBUG_TRACE == BUFFER_TRACE_OFFSET) |
3a2c43579200
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Mychaela Falconia <falcon@freecalypso.org>
parents:
15
diff
changeset
|
766 buffer_trace(2, offset_serv,l1s.actual_time.fn,0,0); |
3a2c43579200
l1p_driv.c: initial import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
15
diff
changeset
|
767 #endif |
3a2c43579200
l1p_driv.c: initial import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
15
diff
changeset
|
768 #endif |
3a2c43579200
l1p_driv.c: initial import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
15
diff
changeset
|
769 } |
3a2c43579200
l1p_driv.c: initial import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
15
diff
changeset
|
770 |
3a2c43579200
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Mychaela Falconia <falcon@freecalypso.org>
parents:
15
diff
changeset
|
771 /*-------------------------------------------------------*/ |
3a2c43579200
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Mychaela Falconia <falcon@freecalypso.org>
parents:
15
diff
changeset
|
772 /* l1pddsp_synchro() */ |
3a2c43579200
l1p_driv.c: initial import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
15
diff
changeset
|
773 /*-------------------------------------------------------*/ |
3a2c43579200
l1p_driv.c: initial import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
15
diff
changeset
|
774 /* Parameters : */ |
3a2c43579200
l1p_driv.c: initial import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
15
diff
changeset
|
775 /* Return : */ |
3a2c43579200
l1p_driv.c: initial import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
15
diff
changeset
|
776 /* Functionality : */ |
3a2c43579200
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Mychaela Falconia <falcon@freecalypso.org>
parents:
15
diff
changeset
|
777 /*-------------------------------------------------------*/ |
3a2c43579200
l1p_driv.c: initial import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
15
diff
changeset
|
778 void l1pddsp_synchro(UWORD8 switch_mode, UWORD8 camp_timeslot) |
3a2c43579200
l1p_driv.c: initial import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
15
diff
changeset
|
779 { |
3a2c43579200
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Mychaela Falconia <falcon@freecalypso.org>
parents:
15
diff
changeset
|
780 // Set "b_abort" to TRUE. |
3a2c43579200
l1p_driv.c: initial import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
15
diff
changeset
|
781 l1s_dsp_com.dsp_db_w_ptr->d_ctrl_system |= (1 << B_TASK_ABORT); |
3a2c43579200
l1p_driv.c: initial import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
15
diff
changeset
|
782 |
3a2c43579200
l1p_driv.c: initial import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
15
diff
changeset
|
783 // Set switch mode within "b_switch_to_gprs" & "b_switch_to_gms" |
3a2c43579200
l1p_driv.c: initial import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
15
diff
changeset
|
784 l1ps_dsp_com.pdsp_ndb_ptr->d_sched_mode_gprs = (switch_mode << B_SWITCH); |
3a2c43579200
l1p_driv.c: initial import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
15
diff
changeset
|
785 |
3a2c43579200
l1p_driv.c: initial import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
15
diff
changeset
|
786 // In case of a switch to GPRS_SCHEDULER, last_used_txpwr is set to "NO_TXPWR" |
3a2c43579200
l1p_driv.c: initial import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
15
diff
changeset
|
787 // in order to force GSM ramp programming when the MS will switch back to |
3a2c43579200
l1p_driv.c: initial import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
15
diff
changeset
|
788 // GSM_SCHEDULER |
3a2c43579200
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Mychaela Falconia <falcon@freecalypso.org>
parents:
15
diff
changeset
|
789 // Moreover, the d_win_start_gprs register must be initialized only during the |
3a2c43579200
l1p_driv.c: initial import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
15
diff
changeset
|
790 // GSM->GPRS switch too. |
3a2c43579200
l1p_driv.c: initial import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
15
diff
changeset
|
791 if(switch_mode == GPRS_SCHEDULER) |
3a2c43579200
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Mychaela Falconia <falcon@freecalypso.org>
parents:
15
diff
changeset
|
792 { |
3a2c43579200
l1p_driv.c: initial import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
15
diff
changeset
|
793 l1s.last_used_txpwr = NO_TXPWR; |
3a2c43579200
l1p_driv.c: initial import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
15
diff
changeset
|
794 |
3a2c43579200
l1p_driv.c: initial import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
15
diff
changeset
|
795 // Set camp timeslot. |
3a2c43579200
l1p_driv.c: initial import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
15
diff
changeset
|
796 l1ps_dsp_com.pdsp_ndb_ptr->d_win_start_gprs = camp_timeslot; |
3a2c43579200
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Mychaela Falconia <falcon@freecalypso.org>
parents:
15
diff
changeset
|
797 } |
3a2c43579200
l1p_driv.c: initial import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
15
diff
changeset
|
798 } |
3a2c43579200
l1p_driv.c: initial import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
15
diff
changeset
|
799 |
3a2c43579200
l1p_driv.c: initial import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
15
diff
changeset
|
800 |
3a2c43579200
l1p_driv.c: initial import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
15
diff
changeset
|
801 /*-------------------------------------------------------*/ |
3a2c43579200
l1p_driv.c: initial import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
15
diff
changeset
|
802 /* l1pddsp_idle_prach_data() */ |
3a2c43579200
l1p_driv.c: initial import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
15
diff
changeset
|
803 /*-------------------------------------------------------*/ |
3a2c43579200
l1p_driv.c: initial import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
15
diff
changeset
|
804 /* Parameters : */ |
3a2c43579200
l1p_driv.c: initial import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
15
diff
changeset
|
805 /* Return : */ |
3a2c43579200
l1p_driv.c: initial import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
15
diff
changeset
|
806 /* Functionality : */ |
3a2c43579200
l1p_driv.c: initial import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
15
diff
changeset
|
807 /*-------------------------------------------------------*/ |
3a2c43579200
l1p_driv.c: initial import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
15
diff
changeset
|
808 void l1pddsp_idle_prach_data(BOOL polling, |
3a2c43579200
l1p_driv.c: initial import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
15
diff
changeset
|
809 UWORD8 cs_type, |
3a2c43579200
l1p_driv.c: initial import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
15
diff
changeset
|
810 UWORD16 channel_request_data, |
3a2c43579200
l1p_driv.c: initial import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
15
diff
changeset
|
811 UWORD8 bsic, |
3a2c43579200
l1p_driv.c: initial import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
15
diff
changeset
|
812 UWORD16 radio_freq) |
3a2c43579200
l1p_driv.c: initial import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
15
diff
changeset
|
813 { |
3a2c43579200
l1p_driv.c: initial import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
15
diff
changeset
|
814 UWORD16 swap_bit; // 16 bit wide to allow shift left. |
3a2c43579200
l1p_driv.c: initial import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
15
diff
changeset
|
815 |
3a2c43579200
l1p_driv.c: initial import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
15
diff
changeset
|
816 // UL on TS=3. |
3a2c43579200
l1p_driv.c: initial import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
15
diff
changeset
|
817 l1ps_dsp_com.pdsp_db_w_ptr->d_task_u_gprs |= 0x80 >> 3; |
3a2c43579200
l1p_driv.c: initial import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
15
diff
changeset
|
818 |
3a2c43579200
l1p_driv.c: initial import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
15
diff
changeset
|
819 // Swap I/Q management. |
3a2c43579200
l1p_driv.c: initial import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
15
diff
changeset
|
820 swap_bit = l1ps_swap_iq_ul(radio_freq); |
3a2c43579200
l1p_driv.c: initial import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
15
diff
changeset
|
821 l1ps_dsp_com.pdsp_db_w_ptr->d_task_u_gprs |= swap_bit << 15; |
3a2c43579200
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Mychaela Falconia <falcon@freecalypso.org>
parents:
15
diff
changeset
|
822 |
3a2c43579200
l1p_driv.c: initial import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
15
diff
changeset
|
823 // Load UL buffer according to "polling" bit. |
3a2c43579200
l1p_driv.c: initial import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
15
diff
changeset
|
824 if(polling) |
3a2c43579200
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Mychaela Falconia <falcon@freecalypso.org>
parents:
15
diff
changeset
|
825 { |
3a2c43579200
l1p_driv.c: initial import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
15
diff
changeset
|
826 // Select first UL polling buffer. |
3a2c43579200
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Mychaela Falconia <falcon@freecalypso.org>
parents:
15
diff
changeset
|
827 l1ps_dsp_com.pdsp_ndb_ptr->a_ul_buffer_gprs[3] = 8; |
3a2c43579200
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Mychaela Falconia <falcon@freecalypso.org>
parents:
15
diff
changeset
|
828 |
3a2c43579200
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Mychaela Falconia <falcon@freecalypso.org>
parents:
15
diff
changeset
|
829 // Store CS type. |
3a2c43579200
l1p_driv.c: initial import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
15
diff
changeset
|
830 l1ps_dsp_com.pdsp_ndb_ptr->a_pu_gprs[0][0] = cs_type; |
3a2c43579200
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Mychaela Falconia <falcon@freecalypso.org>
parents:
15
diff
changeset
|
831 |
3a2c43579200
l1p_driv.c: initial import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
15
diff
changeset
|
832 // Store UL data block. |
3a2c43579200
l1p_driv.c: initial import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
15
diff
changeset
|
833 if(cs_type == CS_PAB8_TYPE) |
3a2c43579200
l1p_driv.c: initial import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
15
diff
changeset
|
834 { |
3a2c43579200
l1p_driv.c: initial import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
15
diff
changeset
|
835 l1ps_dsp_com.pdsp_ndb_ptr->a_pu_gprs[0][2] = ((API)(bsic << 2)) | |
3a2c43579200
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Mychaela Falconia <falcon@freecalypso.org>
parents:
15
diff
changeset
|
836 ((API)(channel_request_data) << 8); |
3a2c43579200
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Mychaela Falconia <falcon@freecalypso.org>
parents:
15
diff
changeset
|
837 l1ps_dsp_com.pdsp_ndb_ptr->a_pu_gprs[0][3] = 0; |
3a2c43579200
l1p_driv.c: initial import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
15
diff
changeset
|
838 } |
3a2c43579200
l1p_driv.c: initial import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
15
diff
changeset
|
839 else |
3a2c43579200
l1p_driv.c: initial import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
15
diff
changeset
|
840 { |
3a2c43579200
l1p_driv.c: initial import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
15
diff
changeset
|
841 l1ps_dsp_com.pdsp_ndb_ptr->a_pu_gprs[0][2] = ((API)(channel_request_data) << 5); |
3a2c43579200
l1p_driv.c: initial import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
15
diff
changeset
|
842 l1ps_dsp_com.pdsp_ndb_ptr->a_pu_gprs[0][3] = ((API)(bsic << 10)); |
3a2c43579200
l1p_driv.c: initial import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
15
diff
changeset
|
843 } |
3a2c43579200
l1p_driv.c: initial import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
15
diff
changeset
|
844 } |
3a2c43579200
l1p_driv.c: initial import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
15
diff
changeset
|
845 else |
3a2c43579200
l1p_driv.c: initial import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
15
diff
changeset
|
846 { |
3a2c43579200
l1p_driv.c: initial import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
15
diff
changeset
|
847 // Set "b_access_prach" to indicate 1 Prach only to DSP. |
3a2c43579200
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Mychaela Falconia <falcon@freecalypso.org>
parents:
15
diff
changeset
|
848 l1ps_dsp_com.pdsp_db_w_ptr->d_task_u_gprs |= (1 << B_ACCESS_PRACH); |
3a2c43579200
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Mychaela Falconia <falcon@freecalypso.org>
parents:
15
diff
changeset
|
849 |
3a2c43579200
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Mychaela Falconia <falcon@freecalypso.org>
parents:
15
diff
changeset
|
850 // Select first UL data buffer. |
3a2c43579200
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Mychaela Falconia <falcon@freecalypso.org>
parents:
15
diff
changeset
|
851 l1ps_dsp_com.pdsp_ndb_ptr->a_ul_buffer_gprs[3] = 0; |
3a2c43579200
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Mychaela Falconia <falcon@freecalypso.org>
parents:
15
diff
changeset
|
852 |
3a2c43579200
l1p_driv.c: initial import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
15
diff
changeset
|
853 // Store CS type. |
3a2c43579200
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Mychaela Falconia <falcon@freecalypso.org>
parents:
15
diff
changeset
|
854 l1ps_dsp_com.pdsp_ndb_ptr->a_du_gprs[0][0] = cs_type; |
3a2c43579200
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Mychaela Falconia <falcon@freecalypso.org>
parents:
15
diff
changeset
|
855 |
3a2c43579200
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Mychaela Falconia <falcon@freecalypso.org>
parents:
15
diff
changeset
|
856 // Store UL data block. |
3a2c43579200
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Mychaela Falconia <falcon@freecalypso.org>
parents:
15
diff
changeset
|
857 if(cs_type == CS_PAB8_TYPE) |
3a2c43579200
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Mychaela Falconia <falcon@freecalypso.org>
parents:
15
diff
changeset
|
858 { |
3a2c43579200
l1p_driv.c: initial import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
15
diff
changeset
|
859 l1ps_dsp_com.pdsp_ndb_ptr->a_du_gprs[0][1] = ((API)(bsic << 2)) | |
3a2c43579200
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Mychaela Falconia <falcon@freecalypso.org>
parents:
15
diff
changeset
|
860 ((API)(channel_request_data) << 8); |
3a2c43579200
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Mychaela Falconia <falcon@freecalypso.org>
parents:
15
diff
changeset
|
861 l1ps_dsp_com.pdsp_ndb_ptr->a_du_gprs[0][2] = 0; |
3a2c43579200
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Mychaela Falconia <falcon@freecalypso.org>
parents:
15
diff
changeset
|
862 } |
3a2c43579200
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Mychaela Falconia <falcon@freecalypso.org>
parents:
15
diff
changeset
|
863 else |
3a2c43579200
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Mychaela Falconia <falcon@freecalypso.org>
parents:
15
diff
changeset
|
864 { |
3a2c43579200
l1p_driv.c: initial import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
15
diff
changeset
|
865 l1ps_dsp_com.pdsp_ndb_ptr->a_du_gprs[0][1] = ((API)(channel_request_data) << 5); |
3a2c43579200
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Mychaela Falconia <falcon@freecalypso.org>
parents:
15
diff
changeset
|
866 l1ps_dsp_com.pdsp_ndb_ptr->a_du_gprs[0][2] = ((API)(bsic << 10)); |
3a2c43579200
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Mychaela Falconia <falcon@freecalypso.org>
parents:
15
diff
changeset
|
867 } |
3a2c43579200
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Mychaela Falconia <falcon@freecalypso.org>
parents:
15
diff
changeset
|
868 |
3a2c43579200
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Mychaela Falconia <falcon@freecalypso.org>
parents:
15
diff
changeset
|
869 if (l1pa_l1ps_com.pra_info.prach_alloc == FIX_PRACH_ALLOC) |
3a2c43579200
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Mychaela Falconia <falcon@freecalypso.org>
parents:
15
diff
changeset
|
870 { |
3a2c43579200
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Mychaela Falconia <falcon@freecalypso.org>
parents:
15
diff
changeset
|
871 // Set fix alloc bit. |
3a2c43579200
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Mychaela Falconia <falcon@freecalypso.org>
parents:
15
diff
changeset
|
872 l1ps_dsp_com.pdsp_ndb_ptr->d_sched_mode_gprs |= (2 << B_MAC_MODE); |
3a2c43579200
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Mychaela Falconia <falcon@freecalypso.org>
parents:
15
diff
changeset
|
873 } |
3a2c43579200
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Mychaela Falconia <falcon@freecalypso.org>
parents:
15
diff
changeset
|
874 else |
3a2c43579200
l1p_driv.c: initial import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
15
diff
changeset
|
875 { |
3a2c43579200
l1p_driv.c: initial import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
15
diff
changeset
|
876 // Reset MAC mode to dynamic allocation |
3a2c43579200
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Mychaela Falconia <falcon@freecalypso.org>
parents:
15
diff
changeset
|
877 l1ps_dsp_com.pdsp_ndb_ptr->d_sched_mode_gprs &= ~(3 << B_MAC_MODE); |
3a2c43579200
l1p_driv.c: initial import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
15
diff
changeset
|
878 |
3a2c43579200
l1p_driv.c: initial import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
15
diff
changeset
|
879 #if !FF_L1_IT_DSP_USF |
3a2c43579200
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Mychaela Falconia <falcon@freecalypso.org>
parents:
15
diff
changeset
|
880 #if (DSP == 33) || (DSP == 34) || (DSP == 35) || (DSP == 36) || (DSP == 37) || (DSP == 38) || (DSP == 39) |
3a2c43579200
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Mychaela Falconia <falcon@freecalypso.org>
parents:
15
diff
changeset
|
881 // Enable USF vote on timeslot 0 |
3a2c43579200
l1p_driv.c: initial import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
15
diff
changeset
|
882 l1ps_dsp_com.pdsp_ndb_ptr->d_usf_vote_enable = 0x80; |
3a2c43579200
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Mychaela Falconia <falcon@freecalypso.org>
parents:
15
diff
changeset
|
883 #endif |
3a2c43579200
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Mychaela Falconia <falcon@freecalypso.org>
parents:
15
diff
changeset
|
884 #endif |
3a2c43579200
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Mychaela Falconia <falcon@freecalypso.org>
parents:
15
diff
changeset
|
885 } |
3a2c43579200
l1p_driv.c: initial import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
15
diff
changeset
|
886 } |
3a2c43579200
l1p_driv.c: initial import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
15
diff
changeset
|
887 } |
3a2c43579200
l1p_driv.c: initial import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
15
diff
changeset
|
888 |
3a2c43579200
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Mychaela Falconia <falcon@freecalypso.org>
parents:
15
diff
changeset
|
889 /*-------------------------------------------------------*/ |
3a2c43579200
l1p_driv.c: initial import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
15
diff
changeset
|
890 /* l1pddsp_idle_prach_power() */ |
3a2c43579200
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Mychaela Falconia <falcon@freecalypso.org>
parents:
15
diff
changeset
|
891 /*-------------------------------------------------------*/ |
3a2c43579200
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Mychaela Falconia <falcon@freecalypso.org>
parents:
15
diff
changeset
|
892 /* Parameters : */ |
3a2c43579200
l1p_driv.c: initial import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
15
diff
changeset
|
893 /* Return : */ |
3a2c43579200
l1p_driv.c: initial import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
15
diff
changeset
|
894 /* Functionality : */ |
3a2c43579200
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Mychaela Falconia <falcon@freecalypso.org>
parents:
15
diff
changeset
|
895 /*-------------------------------------------------------*/ |
3a2c43579200
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Mychaela Falconia <falcon@freecalypso.org>
parents:
15
diff
changeset
|
896 void l1pddsp_idle_prach_power(UWORD8 txpwr, |
3a2c43579200
l1p_driv.c: initial import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
15
diff
changeset
|
897 UWORD16 radio_freq, |
3a2c43579200
l1p_driv.c: initial import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
15
diff
changeset
|
898 UWORD8 ts) |
3a2c43579200
l1p_driv.c: initial import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
15
diff
changeset
|
899 { |
3a2c43579200
l1p_driv.c: initial import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
15
diff
changeset
|
900 #if ((ANLG_FAM == 1) || (ANLG_FAM == 2) || (ANLG_FAM == 3) || (RF_FAM == 61)) |
3a2c43579200
l1p_driv.c: initial import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
15
diff
changeset
|
901 UWORD16 pwr_data; |
3a2c43579200
l1p_driv.c: initial import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
15
diff
changeset
|
902 #endif |
3a2c43579200
l1p_driv.c: initial import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
15
diff
changeset
|
903 |
3a2c43579200
l1p_driv.c: initial import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
15
diff
changeset
|
904 #if ((ANLG_FAM == 1) || (ANLG_FAM == 2) || (ANLG_FAM == 3) ) |
3a2c43579200
l1p_driv.c: initial import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
15
diff
changeset
|
905 // Force FIXED transmit power if requested. |
3a2c43579200
l1p_driv.c: initial import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
15
diff
changeset
|
906 if(l1_config.tx_pwr_code == 0) |
3a2c43579200
l1p_driv.c: initial import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
15
diff
changeset
|
907 { |
3a2c43579200
l1p_driv.c: initial import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
15
diff
changeset
|
908 l1ps_dsp_com.pdsp_db_w_ptr->a_ctrl_power_gprs[ts] = l1_config.params.fixed_txpwr; |
3a2c43579200
l1p_driv.c: initial import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
15
diff
changeset
|
909 |
3a2c43579200
l1p_driv.c: initial import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
15
diff
changeset
|
910 // Control bitmap: update RAMP, use RAMP[5][..]. |
3a2c43579200
l1p_driv.c: initial import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
15
diff
changeset
|
911 l1ps_dsp_com.pdsp_db_w_ptr->a_ctrl_abb_gprs[ts] = |
3a2c43579200
l1p_driv.c: initial import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
15
diff
changeset
|
912 ((1 << B_RAMP_GPRS) | (5 << B_RAMP_NB_GPRS) | (1 << B_BULRAMPDEL) | (1 << B_BULRAMPDEL2)); |
3a2c43579200
l1p_driv.c: initial import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
15
diff
changeset
|
913 |
3a2c43579200
l1p_driv.c: initial import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
15
diff
changeset
|
914 // Store Ramp. |
3a2c43579200
l1p_driv.c: initial import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
15
diff
changeset
|
915 #if (CODE_VERSION != SIMULATION) |
3a2c43579200
l1p_driv.c: initial import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
15
diff
changeset
|
916 Cust_get_ramp_tab(l1ps_dsp_com.pdsp_ndb_ptr->a_ramp_gprs[5], |
3a2c43579200
l1p_driv.c: initial import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
15
diff
changeset
|
917 0, /* not used */ |
3a2c43579200
l1p_driv.c: initial import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
15
diff
changeset
|
918 0, /* not used */ |
3a2c43579200
l1p_driv.c: initial import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
15
diff
changeset
|
919 1 /* arbitrary value for arfcn */ ); |
3a2c43579200
l1p_driv.c: initial import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
15
diff
changeset
|
920 #endif |
3a2c43579200
l1p_driv.c: initial import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
15
diff
changeset
|
921 } |
3a2c43579200
l1p_driv.c: initial import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
15
diff
changeset
|
922 else |
3a2c43579200
l1p_driv.c: initial import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
15
diff
changeset
|
923 { |
3a2c43579200
l1p_driv.c: initial import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
15
diff
changeset
|
924 // Get H/W value corresponding to txpwr command. |
3a2c43579200
l1p_driv.c: initial import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
15
diff
changeset
|
925 pwr_data = Cust_get_pwr_data(txpwr, radio_freq |
3a2c43579200
l1p_driv.c: initial import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
15
diff
changeset
|
926 #if(REL99 && FF_PRF) |
3a2c43579200
l1p_driv.c: initial import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
15
diff
changeset
|
927 ,1 |
3a2c43579200
l1p_driv.c: initial import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
15
diff
changeset
|
928 #endif |
3a2c43579200
l1p_driv.c: initial import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
15
diff
changeset
|
929 ); |
3a2c43579200
l1p_driv.c: initial import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
15
diff
changeset
|
930 |
3a2c43579200
l1p_driv.c: initial import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
15
diff
changeset
|
931 // Store Transmit power. |
3a2c43579200
l1p_driv.c: initial import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
15
diff
changeset
|
932 l1ps_dsp_com.pdsp_db_w_ptr->a_ctrl_power_gprs[ts] = ((pwr_data << 6) | 0x12); |
3a2c43579200
l1p_driv.c: initial import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
15
diff
changeset
|
933 |
3a2c43579200
l1p_driv.c: initial import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
15
diff
changeset
|
934 // Control bitmap: update RAMP, use RAMP[5][..]. |
3a2c43579200
l1p_driv.c: initial import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
15
diff
changeset
|
935 l1ps_dsp_com.pdsp_db_w_ptr->a_ctrl_abb_gprs[ts] = ((1 << B_RAMP_GPRS) | (5 << B_RAMP_NB_GPRS) | (1 << B_BULRAMPDEL) | (1 << B_BULRAMPDEL2)); |
3a2c43579200
l1p_driv.c: initial import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
15
diff
changeset
|
936 |
3a2c43579200
l1p_driv.c: initial import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
15
diff
changeset
|
937 // Store Ramp. |
3a2c43579200
l1p_driv.c: initial import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
15
diff
changeset
|
938 #if (CODE_VERSION != SIMULATION) |
3a2c43579200
l1p_driv.c: initial import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
15
diff
changeset
|
939 Cust_get_ramp_tab(&(l1ps_dsp_com.pdsp_ndb_ptr->a_ramp_gprs[5][0]), txpwr, txpwr, radio_freq); |
3a2c43579200
l1p_driv.c: initial import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
15
diff
changeset
|
940 #endif |
3a2c43579200
l1p_driv.c: initial import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
15
diff
changeset
|
941 } |
3a2c43579200
l1p_driv.c: initial import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
15
diff
changeset
|
942 #endif |
3a2c43579200
l1p_driv.c: initial import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
15
diff
changeset
|
943 |
3a2c43579200
l1p_driv.c: initial import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
15
diff
changeset
|
944 #if (RF_FAM == 61) |
3a2c43579200
l1p_driv.c: initial import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
15
diff
changeset
|
945 // Force FIXED transmit power if requested. |
3a2c43579200
l1p_driv.c: initial import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
15
diff
changeset
|
946 if(l1_config.tx_pwr_code == 0) |
3a2c43579200
l1p_driv.c: initial import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
15
diff
changeset
|
947 { |
3a2c43579200
l1p_driv.c: initial import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
15
diff
changeset
|
948 l1ps_dsp_com.pdsp_db_w_ptr->a_ctrl_power_gprs[ts] = l1_config.params.fixed_txpwr; |
3a2c43579200
l1p_driv.c: initial import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
15
diff
changeset
|
949 |
3a2c43579200
l1p_driv.c: initial import from LoCosto source
Mychaela Falconia <falcon@freecalypso.org>
parents:
15
diff
changeset
|
950 // Control bitmap: update RAMP, use RAMP[5][..]. |
3a2c43579200
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951 l1ps_dsp_com.pdsp_db_w_ptr->a_ctrl_abb_gprs[ts] = |
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952 ((1 << B_RAMP_GPRS) | (5 << B_RAMP_NB_GPRS) | (1 << B_BULRAMPDEL) | (1 << B_BULRAMPDEL2)); |
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953 |
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954 // Store Ramp. |
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955 #if (DSP ==38) || (DSP == 39) |
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956 Cust_get_ramp_tab(l1ps_dsp_com.pdsp_ndb_ptr->a_drp_ramp2_gprs[5], |
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|
957 0, /* not used */ |
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958 0, /* not used */ |
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959 1 /* arbitrary value for arfcn */ ); |
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960 #endif |
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961 } |
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|
962 else |
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|
963 { |
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964 // Get H/W value corresponding to txpwr command. |
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965 pwr_data = Cust_get_pwr_data(txpwr, radio_freq |
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966 #if(REL99 && FF_PRF) |
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967 ,1 |
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968 #endif |
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969 ); |
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|
970 |
3a2c43579200
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changeset
|
971 // Store Transmit power. |
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972 l1ps_dsp_com.pdsp_db_w_ptr->a_ctrl_power_gprs[ts] = (API) (pwr_data); |
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diff
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|
973 |
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974 // Control bitmap: update RAMP, use RAMP[5][..]. |
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|
975 l1ps_dsp_com.pdsp_db_w_ptr->a_ctrl_abb_gprs[ts] = ((1 << B_RAMP_GPRS) | (5 << B_RAMP_NB_GPRS) | (1 << B_BULRAMPDEL) | (1 << B_BULRAMPDEL2)); |
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|
976 |
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977 // Store Ramp. |
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|
978 #if(DSP == 38) || (DSP == 39) |
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|
979 Cust_get_ramp_tab(&(l1ps_dsp_com.pdsp_ndb_ptr->a_drp_ramp2_gprs[5][0]), txpwr, txpwr, radio_freq); |
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980 #endif |
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|
981 } |
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982 #endif //RF_FAM == 61 |
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|
983 |
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984 } |
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|
985 |
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changeset
|
986 /*-------------------------------------------------------*/ |
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|
987 /* l1pddsp_single_block() */ |
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988 /*-------------------------------------------------------*/ |
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989 /* Parameters : */ |
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|
990 /* Return : */ |
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changeset
|
991 /* Functionality : */ |
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992 /*-------------------------------------------------------*/ |
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993 void l1pddsp_single_tx_block(UWORD8 burst_nb, |
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994 UWORD8 *data, |
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|
995 UWORD8 tsc, |
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996 UWORD16 radio_freq) |
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|
997 { |
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998 UWORD16 swap_bit; // 16 bit wide to allow shift left. |
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|
999 |
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changeset
|
1000 // Burst number within a block. |
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1001 l1ps_dsp_com.pdsp_db_w_ptr->d_burst_nb_gprs = burst_nb; |
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1002 |
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1003 // UL on TS=3. |
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1004 l1ps_dsp_com.pdsp_db_w_ptr->d_task_u_gprs |= 0x80 >> 3; |
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|
1005 |
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1006 // Swap I/Q management. |
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1007 swap_bit = l1ps_swap_iq_ul(radio_freq); |
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1008 l1ps_dsp_com.pdsp_db_w_ptr->d_task_u_gprs |= swap_bit << 15; |
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1009 |
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|
1010 // Select first UL polling buffer. |
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1011 l1ps_dsp_com.pdsp_ndb_ptr->a_ul_buffer_gprs[3] = 8; |
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1012 |
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1013 // Store CS type: CS1 for Polling. |
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1014 l1ps_dsp_com.pdsp_ndb_ptr->a_pu_gprs[0][0] = CS1_TYPE_POLL; |
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|
1015 |
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1016 if(burst_nb == BURST_1) |
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1017 // Store UL data block. |
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|
1018 { |
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|
1019 API *ul_block_ptr = &(l1ps_dsp_com.pdsp_ndb_ptr->a_pu_gprs[0][2]); |
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|
1020 UWORD8 i,j; |
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|
1021 |
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|
1022 // Copy first 22 bytes in the first 11 words after header. |
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1023 for (i=0, j=0; j<11; j++) |
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1024 { |
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1025 ul_block_ptr[j] = ((API)(data[i])) | ((API)(data[i+1]) << 8); |
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1026 i += 2; |
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|
1027 } |
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1028 // Copy last UWORD8 (23rd) in the 12th word after header. |
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|
1029 ul_block_ptr[11] = data[22]; |
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|
1030 } |
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|
1031 |
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|
1032 // Training sequence. |
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1033 // Rem: bcch_freq_ind is set within Hopping algo. |
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|
1034 l1s_dsp_com.dsp_db_w_ptr->d_ctrl_system |= tsc << B_TSQ; |
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|
1035 } |
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|
1036 |
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|
1037 /*-------------------------------------------------------*/ |
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|
1038 /* l1pddsp_idle_rx_nb() */ |
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1039 /*-------------------------------------------------------*/ |
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1040 /* Parameters : */ |
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|
1041 /* Return : */ |
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|
1042 /* Functionality : */ |
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1043 /*-------------------------------------------------------*/ |
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|
1044 #if FF_L1_IT_DSP_USF |
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1045 void l1pddsp_idle_rx_nb(UWORD8 burst_nb, |
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1046 UWORD8 tsc, |
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1047 UWORD16 radio_freq, |
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|
1048 UWORD8 timeslot_no, |
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1049 BOOL ptcch_dl, |
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|
1050 BOOL usf_interrupt) |
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1051 #else |
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|
1052 void l1pddsp_idle_rx_nb(UWORD8 burst_nb, |
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|
1053 UWORD8 tsc, |
3a2c43579200
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|
1054 UWORD16 radio_freq, |
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|
1055 UWORD8 timeslot_no, |
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changeset
|
1056 BOOL ptcch_dl) |
3a2c43579200
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diff
changeset
|
1057 #endif |
3a2c43579200
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15
diff
changeset
|
1058 { |
3a2c43579200
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15
diff
changeset
|
1059 UWORD16 swap_bit; // 16 bit wide to allow shift left. |
3a2c43579200
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Mychaela Falconia <falcon@freecalypso.org>
parents:
15
diff
changeset
|
1060 |
3a2c43579200
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15
diff
changeset
|
1061 // DL on TS=0. |
3a2c43579200
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15
diff
changeset
|
1062 l1ps_dsp_com.pdsp_db_w_ptr->d_task_d_gprs |= 0x80 >> timeslot_no; |
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Mychaela Falconia <falcon@freecalypso.org>
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15
diff
changeset
|
1063 |
3a2c43579200
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15
diff
changeset
|
1064 // Swap I/Q management. |
3a2c43579200
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15
diff
changeset
|
1065 swap_bit = l1ps_swap_iq_dl(radio_freq); |
3a2c43579200
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diff
changeset
|
1066 l1ps_dsp_com.pdsp_db_w_ptr->d_task_d_gprs |= swap_bit << 15; |
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parents:
15
diff
changeset
|
1067 |
3a2c43579200
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diff
changeset
|
1068 if(ptcch_dl) |
3a2c43579200
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Mychaela Falconia <falcon@freecalypso.org>
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15
diff
changeset
|
1069 { |
3a2c43579200
l1p_driv.c: initial import from LoCosto source
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15
diff
changeset
|
1070 // PTCCH/DL case must be flagged to DSP. |
3a2c43579200
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parents:
15
diff
changeset
|
1071 l1ps_dsp_com.pdsp_db_w_ptr->d_task_d_gprs |= (1 << B_PTCCH_DL); |
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parents:
15
diff
changeset
|
1072 } |
3a2c43579200
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Mychaela Falconia <falcon@freecalypso.org>
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15
diff
changeset
|
1073 |
3a2c43579200
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parents:
15
diff
changeset
|
1074 // Burst number within a block. |
3a2c43579200
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parents:
15
diff
changeset
|
1075 l1ps_dsp_com.pdsp_db_w_ptr->d_burst_nb_gprs = burst_nb; |
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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changeset
|
1076 |
3a2c43579200
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parents:
15
diff
changeset
|
1077 // Channel coding is forced to CS1. |
3a2c43579200
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15
diff
changeset
|
1078 l1ps_dsp_com.pdsp_ndb_ptr->a_ctrl_ched_gprs[timeslot_no] = CS1_TYPE_DATA; |
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parents:
15
diff
changeset
|
1079 |
3a2c43579200
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diff
changeset
|
1080 // pass information to DSP which good USF value is to be expected |
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changeset
|
1081 l1ps_dsp_com.pdsp_ndb_ptr->a_usf_gprs[0] = (API) 0x07; |
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changeset
|
1082 |
3a2c43579200
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changeset
|
1083 #if FF_L1_IT_DSP_USF |
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changeset
|
1084 // In case of connection establishment mode with dynamic or fixed |
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15
diff
changeset
|
1085 // allocation scheme we need to request the DSP USF interrupt for PRACH |
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diff
changeset
|
1086 // scheduling. Latched by DSP during Work3 |
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diff
changeset
|
1087 if (burst_nb == 3) |
3a2c43579200
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Mychaela Falconia <falcon@freecalypso.org>
parents:
15
diff
changeset
|
1088 { |
3a2c43579200
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Mychaela Falconia <falcon@freecalypso.org>
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diff
changeset
|
1089 if (usf_interrupt) |
3a2c43579200
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diff
changeset
|
1090 l1ps_dsp_com.pdsp_ndb_ptr->d_usf_vote_enable |= (1 << B_USF_IT); |
3a2c43579200
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parents:
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diff
changeset
|
1091 else |
3a2c43579200
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15
diff
changeset
|
1092 l1ps_dsp_com.pdsp_ndb_ptr->d_usf_vote_enable &= ~(1 << B_USF_IT); |
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parents:
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diff
changeset
|
1093 } |
3a2c43579200
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15
diff
changeset
|
1094 #endif |
3a2c43579200
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changeset
|
1095 |
3a2c43579200
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parents:
15
diff
changeset
|
1096 // RIF receiver algorithm: select 156.25. |
3a2c43579200
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parents:
15
diff
changeset
|
1097 l1ps_dsp_com.pdsp_ndb_ptr->d_sched_mode_gprs &= 0xFFFF ^ (1 << B_RIF_RX_MODE); |
3a2c43579200
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parents:
15
diff
changeset
|
1098 |
3a2c43579200
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Mychaela Falconia <falcon@freecalypso.org>
parents:
15
diff
changeset
|
1099 // Training sequence. |
3a2c43579200
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Mychaela Falconia <falcon@freecalypso.org>
parents:
15
diff
changeset
|
1100 // Rem: bcch_freq_ind is set within Hopping algo. |
3a2c43579200
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Mychaela Falconia <falcon@freecalypso.org>
parents:
15
diff
changeset
|
1101 l1s_dsp_com.dsp_db_w_ptr->d_ctrl_system |= tsc << B_TSQ; |
3a2c43579200
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Mychaela Falconia <falcon@freecalypso.org>
parents:
15
diff
changeset
|
1102 |
3a2c43579200
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changeset
|
1103 } |
3a2c43579200
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diff
changeset
|
1104 |
3a2c43579200
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changeset
|
1105 |
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changeset
|
1106 /*-------------------------------------------------------*/ |
3a2c43579200
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diff
changeset
|
1107 /* l1pddsp_transfer_mslot_ctrl() */ |
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changeset
|
1108 /*-------------------------------------------------------*/ |
3a2c43579200
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|
1109 /* Parameters : */ |
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|
1110 /* Return : */ |
3a2c43579200
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|
1111 /* Functionality : */ |
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|
1112 /*-------------------------------------------------------*/ |
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changeset
|
1113 void l1pddsp_transfer_mslot_ctrl(UWORD8 burst_nb, |
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|
1114 UWORD8 dl_bitmap, |
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|
1115 UWORD8 ul_bitmap, |
3a2c43579200
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|
1116 UWORD8 *usf_table, |
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|
1117 UWORD8 mac_mode, |
3a2c43579200
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changeset
|
1118 UWORD8 *ul_buffer_index, |
3a2c43579200
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|
1119 UWORD8 tsc, |
3a2c43579200
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|
1120 UWORD16 radio_freq, |
3a2c43579200
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|
1121 UWORD8 synchro_timeslot, |
3a2c43579200
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changeset
|
1122 #if FF_L1_IT_DSP_USF |
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changeset
|
1123 UWORD8 dsp_usf_interrupt |
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changeset
|
1124 #else |
3a2c43579200
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|
1125 UWORD8 usf_vote_enable |
3a2c43579200
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changeset
|
1126 #endif |
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|
1127 ) |
3a2c43579200
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changeset
|
1128 { |
3a2c43579200
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|
1129 UWORD8 i; |
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|
1130 UWORD16 swap_bit; // 16 bit wide to allow shift left. |
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|
1131 |
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|
1132 // Burst number within a block. |
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changeset
|
1133 l1ps_dsp_com.pdsp_db_w_ptr->d_burst_nb_gprs = burst_nb; |
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changeset
|
1134 |
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|
1135 // DL bitmap. |
3a2c43579200
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changeset
|
1136 l1ps_dsp_com.pdsp_db_w_ptr->d_task_d_gprs = dl_bitmap; |
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changeset
|
1137 |
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changeset
|
1138 // UL bitmap. |
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changeset
|
1139 l1ps_dsp_com.pdsp_db_w_ptr->d_task_u_gprs = ul_bitmap; |
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changeset
|
1140 |
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changeset
|
1141 // Swap I/Q management for DL. |
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changeset
|
1142 swap_bit = l1ps_swap_iq_dl(radio_freq); |
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changeset
|
1143 l1ps_dsp_com.pdsp_db_w_ptr->d_task_d_gprs |= swap_bit << 15; |
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changeset
|
1144 |
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changeset
|
1145 // Swap I/Q management for UL. |
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changeset
|
1146 swap_bit = l1ps_swap_iq_ul(radio_freq); |
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changeset
|
1147 l1ps_dsp_com.pdsp_db_w_ptr->d_task_u_gprs |= swap_bit << 15; |
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changeset
|
1148 |
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changeset
|
1149 if(burst_nb == 0) |
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|
1150 { |
3a2c43579200
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changeset
|
1151 // Store USF table |
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changeset
|
1152 for(i=0;i<(8 - synchro_timeslot);i++) |
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changeset
|
1153 l1ps_dsp_com.pdsp_ndb_ptr->a_usf_gprs[i] = usf_table[i+synchro_timeslot]; |
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changeset
|
1154 |
3a2c43579200
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changeset
|
1155 // Automatic CS detection. |
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changeset
|
1156 for(i=0;i<8;i++) |
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changeset
|
1157 { |
3a2c43579200
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changeset
|
1158 l1ps_dsp_com.pdsp_ndb_ptr->a_ctrl_ched_gprs[i] = CS_AUTO_DETECT; |
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diff
changeset
|
1159 |
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changeset
|
1160 // Select first UL polling buffer. |
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1161 l1ps_dsp_com.pdsp_ndb_ptr->a_ul_buffer_gprs[i] = ul_buffer_index[i]; |
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1162 } |
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1163 |
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1164 #if !FF_L1_IT_DSP_USF |
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1165 // USF vote enable programming |
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1166 |
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1167 #if (DSP == 33) || (DSP == 34) || (DSP == 35) || (DSP == 36) || (DSP == 37) || (DSP == 38) || (DSP == 39) |
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1168 // Multislot TX allowed and usf_vote_enable suported: programs usf_vote_enable |
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1169 l1ps_dsp_com.pdsp_ndb_ptr->d_usf_vote_enable = usf_vote_enable; |
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1170 #else |
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1171 // Single slot TX only and usf_vote_enable not supported |
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1172 // Modify MAC mode |
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1173 if (usf_vote_enable) |
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1174 // USF vote enabled --> Set MAC mode to dynamic mode |
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1175 mac_mode = DYN_ALLOC; |
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1176 else |
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1177 // USF vote disabled --> Set MAC mode to fixed mode |
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1178 mac_mode = FIX_ALLOC_NO_HALF; |
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1179 #endif |
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1180 |
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1181 #endif // !FF_L1_IT_DSP_USF |
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1182 |
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1183 // MAC mode. |
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1184 l1ps_dsp_com.pdsp_ndb_ptr->d_sched_mode_gprs &= ~(3 << B_MAC_MODE); |
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1185 l1ps_dsp_com.pdsp_ndb_ptr->d_sched_mode_gprs |= mac_mode << B_MAC_MODE; |
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1186 } |
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1187 |
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1188 #if FF_L1_IT_DSP_USF |
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1189 if(burst_nb == 3) |
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1190 { |
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1191 // Program DSP to generate an interrupt once USF available if |
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1192 // required. Latched by DSP during Work3. |
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1193 if (dsp_usf_interrupt) |
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1194 l1ps_dsp_com.pdsp_ndb_ptr->d_usf_vote_enable = (1 << B_USF_IT); |
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1195 else |
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1196 l1ps_dsp_com.pdsp_ndb_ptr->d_usf_vote_enable = 0; |
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1197 } |
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1198 #endif |
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1199 |
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1200 // RIF receiver algorithm: select 156.25. |
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1201 l1ps_dsp_com.pdsp_ndb_ptr->d_sched_mode_gprs &= 0xFFFF ^ (1 << B_RIF_RX_MODE); |
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1202 |
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1203 // d_fn |
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1204 // ---- |
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1205 // bit [0..7] -> b_fn_report, unused for GPRS |
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1206 // bit [8..15] -> b_fn_sid , FN%104 |
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|
1207 l1s_dsp_com.dsp_db_w_ptr->d_fn = ((l1s.next_time.fn_mod104)<<8); |
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|
1208 |
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1209 // Training sequence. |
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1210 // Rem: bcch_freq_ind is set within Hopping algo. |
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|
1211 l1s_dsp_com.dsp_db_w_ptr->d_ctrl_system |= tsc << B_TSQ; |
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|
1212 |
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1213 } |
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|
1214 |
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|
1215 |
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1216 /*-------------------------------------------------------*/ |
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1217 /* l1pddsp_transfer_mslot_power() */ |
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1218 /*-------------------------------------------------------*/ |
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1219 /* Parameters : */ |
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1220 /* Return : */ |
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|
1221 /* Functionality : */ |
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|
1222 /*-------------------------------------------------------*/ |
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|
1223 void l1pddsp_transfer_mslot_power(UWORD8 *txpwr, |
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|
1224 UWORD16 radio_freq, |
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|
1225 UWORD8 ul_bitmap) |
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|
1226 { |
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|
1227 #define NO_TX 100 |
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|
1228 |
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|
1229 UWORD16 i; // 16 bit needed for shifting pupose. |
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|
1230 UWORD8 last_TX = NO_TX; |
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|
1231 UWORD8 txpwr_ramp_up; |
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|
1232 UWORD8 txpwr_ramp_down; |
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|
1233 UWORD8 cpt_TX = 0; |
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|
1234 UWORD8 ts_mask; |
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|
1235 WORD16 ts_conv; |
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|
1236 |
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|
1237 #if (REL99 && FF_PRF) |
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1238 UWORD8 number_uplink_timeslot = 0 ; // number of uplink timeslot for power reduction feature |
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|
1239 #endif |
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|
1240 |
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|
1241 |
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|
1242 #if ((ANLG_FAM == 1) || (ANLG_FAM == 2) || (ANLG_FAM == 3) || (RF_FAM == 61)) |
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|
1243 UWORD16 pwr_data; |
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|
1244 UWORD16 d_ramp_idx; |
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|
1245 #endif |
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|
1246 |
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|
1247 //Locosto #if ((ANLG_FAM == 1) || (ANLG_FAM == 2) || (ANLG_FAM == 3)) |
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|
1248 |
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|
1249 // This function is called with an ul_bitmap which represents the abolute |
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1250 // position of any Tx bursts in this frame. This bitmap has already |
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|
1251 // absorbed any synchro change (in dl_tn), hence we need to do some |
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1252 // processing to recover the actual Tx timeslot number which is used |
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1253 // as an index into the txpwr array. |
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1254 // |
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1255 // Example : MS Class 8 with 4 Rx and 1 Tx : |
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1256 // |
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1257 // |
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1258 // dl_ts_alloc : 0x0f 0 0 0 0 R R R R |
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1259 // ul_ts_alloc : 0x02 0 0 0 0 0 0 T 0 |
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1260 // shift + combine : 0 0 0 0 R R R R 0 T |
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1261 // set dl_tn=4 : R R R R 0 T 0 0 |
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1262 // ul_bitmap : 0x04 0 0 0 0 0 1 0 0 |
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1263 // i : 5 |
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|
1264 // |
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|
1265 // Example : MS Class 8 with 1 Rx and 1 Tx on TS=7 |
3a2c43579200
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1266 // |
3a2c43579200
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|
1267 // dl_ts_alloc : 0x01 0 0 0 0 0 0 0 R |
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diff
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|
1268 // ul_ts_alloc : 0x01 0 0 0 0 0 0 0 T |
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|
1269 // shift + combine : 0 0 0 0 0 0 0 R 0 0 T |
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|
1270 // set dl_tn=7 : R 0 0 T 0 0 0 0 |
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|
1271 // ul_bitmap : 0x10 0 0 0 1 0 0 0 0 |
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|
1272 // i : 3 |
3a2c43579200
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|
1273 // |
3a2c43579200
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diff
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|
1274 // We recover the actual timeslot from the ul_bitmap by the following |
3a2c43579200
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1275 // method : |
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|
1276 // |
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diff
changeset
|
1277 // ts = (i + dl_tn) - 3 |
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diff
changeset
|
1278 // |
3a2c43579200
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diff
changeset
|
1279 // Where i is the loopindex usd to detect "1" in the ul_bitmap. |
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|
1280 // This works for MS class 8 because (3 <= i <= 5) if the |
3a2c43579200
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changeset
|
1281 // multislot class is respected. |
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diff
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|
1282 |
3a2c43579200
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changeset
|
1283 #if (REL99 && FF_PRF)// power reduction feature |
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changeset
|
1284 for (i=0; i<8; i++) |
3a2c43579200
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diff
changeset
|
1285 { |
3a2c43579200
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diff
changeset
|
1286 // computed number of uplink timeslot in order to determine uplink power reduction |
3a2c43579200
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diff
changeset
|
1287 ts_mask = (0x80>>i); |
3a2c43579200
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15
diff
changeset
|
1288 if (ul_bitmap & ts_mask) |
3a2c43579200
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15
diff
changeset
|
1289 number_uplink_timeslot++; |
3a2c43579200
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diff
changeset
|
1290 } |
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diff
changeset
|
1291 #endif |
3a2c43579200
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15
diff
changeset
|
1292 |
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diff
changeset
|
1293 |
3a2c43579200
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diff
changeset
|
1294 ts_conv = l1a_l1s_com.dl_tn - 3; |
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diff
changeset
|
1295 |
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diff
changeset
|
1296 // Index of the programmed ramps |
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changeset
|
1297 d_ramp_idx = 0; |
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diff
changeset
|
1298 |
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15
diff
changeset
|
1299 for(i=0;i<8;i++) |
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changeset
|
1300 { |
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changeset
|
1301 // Program Transmit power and ramp for allocated timeslots. |
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changeset
|
1302 if(ul_bitmap & (0x80>>i)) |
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changeset
|
1303 { |
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changeset
|
1304 // Fixe transmit power. |
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changeset
|
1305 if(l1_config.tx_pwr_code == 0) |
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|
1306 { |
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changeset
|
1307 // Store Transmit power. |
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changeset
|
1308 l1ps_dsp_com.pdsp_db_w_ptr->a_ctrl_power_gprs[i] = l1_config.params.fixed_txpwr; |
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|
1309 |
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changeset
|
1310 // Control bitmap: update RAMP, use RAMP[d_ramp_idx][..]. |
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|
1311 l1ps_dsp_com.pdsp_db_w_ptr->a_ctrl_abb_gprs[i] = |
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|
1312 ((d_ramp_idx << B_RAMP_NB_GPRS) | (1 << B_RAMP_GPRS) | (1 << B_BULRAMPDEL) | (1 << B_BULRAMPDEL2)); |
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|
1313 |
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|
1314 // Store Ramp. |
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|
1315 #if (RF_FAM == 61) |
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|
1316 #if (DSP ==38) || (DSP == 39) |
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1317 Cust_get_ramp_tab(l1ps_dsp_com.pdsp_ndb_ptr->a_drp_ramp2_gprs[d_ramp_idx++], |
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changeset
|
1318 0, /* not used */ |
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|
1319 0, /* not used */ |
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|
1320 1 /* arbitrary value for arfcn */ ); |
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|
1321 #endif |
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|
1322 #else |
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changeset
|
1323 #if (CODE_VERSION != SIMULATION) |
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|
1324 Cust_get_ramp_tab(l1ps_dsp_com.pdsp_ndb_ptr->a_ramp_gprs[d_ramp_idx++], |
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changeset
|
1325 0, /* not used */ |
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changeset
|
1326 0, /* not used */ |
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diff
changeset
|
1327 1 /* arbitrary value for arfcn */ ); |
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|
1328 #endif |
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changeset
|
1329 #endif |
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|
1330 } |
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|
1331 else |
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diff
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|
1332 { |
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|
1333 // count the number of TX windows |
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|
1334 cpt_TX ++; |
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15
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|
1335 |
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|
1336 // Get power amplifier data. |
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|
1337 #if(REL99 && FF_PRF) |
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|
1338 pwr_data = Cust_get_pwr_data(txpwr[i+ts_conv], radio_freq, number_uplink_timeslot); |
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|
1339 #else |
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|
1340 pwr_data = Cust_get_pwr_data(txpwr[i+ts_conv], radio_freq); |
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|
1341 #endif |
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|
1342 |
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|
1343 |
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|
1344 // Store Transmit power. |
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|
1345 #if(RF_FAM == 61) |
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|
1346 l1ps_dsp_com.pdsp_db_w_ptr->a_ctrl_power_gprs[i] = (pwr_data); |
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|
1347 #else |
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|
1348 l1ps_dsp_com.pdsp_db_w_ptr->a_ctrl_power_gprs[i] = ((pwr_data << 6) | 0x12); |
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|
1349 #endif |
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|
1350 |
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|
1351 // Control bitmap: update RAMP, use RAMP[d_ramp_idx][..] for slot i. |
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1352 l1ps_dsp_com.pdsp_db_w_ptr->a_ctrl_abb_gprs[i] = ((d_ramp_idx << B_RAMP_NB_GPRS) | (1 << B_RAMP_GPRS) | (1 << B_BULRAMPDEL) | (1 << B_BULRAMPDEL2)); |
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|
1353 |
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|
1354 // Store Ramp. |
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1355 // ========== |
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changeset
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1356 // for the 1st TX the RAMP is: RAMP_UP_TX1 / RAMP_DOWN_TX1 |
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1357 // for the 2nd TX the RAMP is: RAMP_UP_TX2 / RAMP_DOWN_TX1 |
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|
1358 // for the 3rd TX the RAMP is: RAMP_UP_TX3 / RAMP_DOWN_TX2 |
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changeset
|
1359 // (...) |
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1360 // for the (i)th TX the RAMP is: RAMP_UP_TX_(i) / RAMP_DOWN_TX_(i-1) |
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|
1361 // for the additionnal RAMP : xxxx / RAMP_DOWN_TX_last |
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|
1362 |
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|
1363 txpwr_ramp_up = txpwr[i+ts_conv]; // the ramp up is the current TX |
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|
1364 |
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1365 if(last_TX == NO_TX) // specific case of the first TX |
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1366 txpwr_ramp_down = txpwr[i+ts_conv]; // the ramp down is the current TX |
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1367 else |
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|
1368 txpwr_ramp_down = txpwr[last_TX+ts_conv]; // the ramp down is the previous TX |
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1369 |
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1370 #if(RF_FAM == 61) |
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1371 #if(DSP == 38) || (DSP == 39) |
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1372 Cust_get_ramp_tab(&(l1ps_dsp_com.pdsp_ndb_ptr->a_drp_ramp2_gprs[d_ramp_idx++][0]), txpwr_ramp_up, txpwr_ramp_down, radio_freq); |
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1373 #endif |
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1374 #else |
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|
1375 #if (CODE_VERSION != SIMULATION) |
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|
1376 Cust_get_ramp_tab(&(l1ps_dsp_com.pdsp_ndb_ptr->a_ramp_gprs[d_ramp_idx++][0]), txpwr_ramp_up, txpwr_ramp_down, radio_freq); |
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|
1377 #endif |
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|
1378 #endif |
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1379 } |
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|
1380 |
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|
1381 // memorize the last TX window |
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|
1382 last_TX = i; |
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1383 } |
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|
1384 else |
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|
1385 { |
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|
1386 // program an interrupt in the TS following |
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|
1387 // the last TX window and needed by the DSP |
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|
1388 |
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|
1389 // Is it the TS following a TX window ? |
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|
1390 if((i == last_TX+1) && (i<8)) |
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|
1391 { |
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|
1392 // program the interrupt |
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|
1393 l1ps_dsp_com.pdsp_db_w_ptr->a_ctrl_abb_gprs[i] = (1 << B_MS_RULE); |
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|
1394 } |
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|
1395 } |
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|
1396 } |
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|
1397 |
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|
1398 // in a multi-TX case an additionnal ramp down must be set |
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|
1399 if(cpt_TX > 1) |
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|
1400 { |
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|
1401 // Control bitmap: update RAMP, use RAMP[d_ramp_idx][..] for slot i and set the interrupt |
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|
1402 if((last_TX+1) <= 7) |
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|
1403 l1ps_dsp_com.pdsp_db_w_ptr->a_ctrl_abb_gprs[last_TX+1] = ((d_ramp_idx << B_RAMP_NB_GPRS) | (1 << B_RAMP_GPRS) | (1 << B_MS_RULE)); |
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|
1404 |
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|
1405 // Store Ramp. |
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|
1406 // ========== |
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|
1407 txpwr_ramp_up = txpwr[last_TX+ts_conv]; // this ramp up is unused (default: set to last_TX) |
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|
1408 txpwr_ramp_down = txpwr[last_TX+ts_conv]; // the ramp down is the last TX |
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|
1409 |
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|
1410 #if(RF_FAM == 61) |
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|
1411 #if(DSP ==38) || (DSP == 39) |
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|
1412 Cust_get_ramp_tab(&(l1ps_dsp_com.pdsp_ndb_ptr->a_drp_ramp2_gprs[d_ramp_idx][0]), txpwr_ramp_up, txpwr_ramp_down, radio_freq); |
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|
1413 #endif |
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|
1414 #else |
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|
1415 #if (CODE_VERSION != SIMULATION) |
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|
1416 Cust_get_ramp_tab(&(l1ps_dsp_com.pdsp_ndb_ptr->a_ramp_gprs[d_ramp_idx][0]), txpwr_ramp_up, txpwr_ramp_down, radio_freq); |
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|
1417 #endif |
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|
1418 #endif |
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|
1419 } |
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|
1420 // #endif Locosto |
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|
1421 } |
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|
1422 |
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diff
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|
1423 |
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|
1424 /*-------------------------------------------------------*/ |
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|
1425 /* l1pddsp_ul_ptcch_data() */ |
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|
1426 /*-------------------------------------------------------*/ |
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|
1427 /* Parameters : */ |
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|
1428 /* Return : */ |
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15
diff
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|
1429 /* Functionality : */ |
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|
1430 /*-------------------------------------------------------*/ |
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|
1431 void l1pddsp_ul_ptcch_data(UWORD8 cs_type, |
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|
1432 UWORD16 channel_request_data, |
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15
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|
1433 UWORD8 bsic, |
3a2c43579200
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15
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|
1434 UWORD16 radio_freq, |
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diff
changeset
|
1435 UWORD8 timeslot_no) |
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diff
changeset
|
1436 { |
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diff
changeset
|
1437 UWORD16 swap_bit; // 16 bit wide to allow shift left. |
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changeset
|
1438 |
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15
diff
changeset
|
1439 // UL on TS=timeslot_no. |
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15
diff
changeset
|
1440 l1ps_dsp_com.pdsp_db_w_ptr->d_task_u_gprs |= 0x80 >> timeslot_no; |
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15
diff
changeset
|
1441 |
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15
diff
changeset
|
1442 // Swap I/Q management. |
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|
1443 swap_bit = l1ps_swap_iq_ul(radio_freq); |
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|
1444 l1ps_dsp_com.pdsp_db_w_ptr->d_task_u_gprs |= swap_bit << 15; |
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15
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|
1445 |
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|
1446 // Set "b_ptcch_ul" to indicate PTCCH/UL to DSP. |
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15
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changeset
|
1447 l1ps_dsp_com.pdsp_db_w_ptr->d_task_u_gprs |= (1 << B_PTCCH_UL); |
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15
diff
changeset
|
1448 |
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diff
changeset
|
1449 // Store CS type. |
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|
1450 l1ps_dsp_com.pdsp_ndb_ptr->a_ptcchu_gprs[0] = cs_type; |
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diff
changeset
|
1451 |
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|
1452 // Store UL data block. |
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changeset
|
1453 if(cs_type == CS_PAB8_TYPE) |
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changeset
|
1454 { |
3a2c43579200
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changeset
|
1455 l1ps_dsp_com.pdsp_ndb_ptr->a_ptcchu_gprs[1] = ((API)(bsic << 2)) | |
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changeset
|
1456 ((API)(channel_request_data) << 8); |
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changeset
|
1457 l1ps_dsp_com.pdsp_ndb_ptr->a_ptcchu_gprs[2] = 0; |
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changeset
|
1458 } |
3a2c43579200
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changeset
|
1459 else |
3a2c43579200
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diff
changeset
|
1460 { |
3a2c43579200
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changeset
|
1461 l1ps_dsp_com.pdsp_ndb_ptr->a_ptcchu_gprs[1] = ((API)(channel_request_data) << 5); |
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changeset
|
1462 l1ps_dsp_com.pdsp_ndb_ptr->a_ptcchu_gprs[2] = ((API)(bsic << 10)); |
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|
1463 } |
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|
1464 } |
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changeset
|
1465 |
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|
1466 |
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|
1467 /*-------------------------------------------------------*/ |
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|
1468 /* l1pddsp_interf_meas_ctrl() */ |
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|
1469 /*-------------------------------------------------------*/ |
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changeset
|
1470 /* Parameters : */ |
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|
1471 /* Return : */ |
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|
1472 /* Functionality : */ |
3a2c43579200
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15
diff
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|
1473 void l1pddsp_interf_meas_ctrl(UWORD8 nb_meas_req) |
3a2c43579200
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15
diff
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|
1474 { |
3a2c43579200
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15
diff
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|
1475 // Interference measurement task set as a monitoring task within GSM interface. |
3a2c43579200
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15
diff
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|
1476 // 101 means 1 meas, 102 means 2 meas ... |
3a2c43579200
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15
diff
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|
1477 // Rem: swap I/Q is not managed for power measurements. |
3a2c43579200
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15
diff
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|
1478 l1s_dsp_com.dsp_db_w_ptr->d_task_md = INTERF_DSP_TASK + nb_meas_req; |
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15
diff
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|
1479 } |
3a2c43579200
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15
diff
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|
1480 |
3a2c43579200
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Mychaela Falconia <falcon@freecalypso.org>
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15
diff
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|
1481 |
3a2c43579200
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15
diff
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|
1482 /*-------------------------------------------------------*/ |
3a2c43579200
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15
diff
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|
1483 /* l1pddsp_transfer_meas_ctrl() */ |
3a2c43579200
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15
diff
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|
1484 /*-------------------------------------------------------*/ |
3a2c43579200
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15
diff
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|
1485 /* Parameters : */ |
3a2c43579200
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15
diff
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|
1486 /* Return : */ |
3a2c43579200
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15
diff
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|
1487 /* Functionality : */ |
3a2c43579200
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15
diff
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|
1488 /*-------------------------------------------------------*/ |
3a2c43579200
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15
diff
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|
1489 void l1pddsp_transfer_meas_ctrl(UWORD8 meas_position) |
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15
diff
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|
1490 { |
3a2c43579200
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15
diff
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|
1491 // Store measurement position. |
3a2c43579200
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15
diff
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|
1492 // Rem: This is a L1S filtered information giving the position of the meas. as a |
3a2c43579200
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diff
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|
1493 // bitmap. |
3a2c43579200
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15
diff
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|
1494 // Rem: swap I/Q is not managed for power measurements. |
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15
diff
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|
1495 l1ps_dsp_com.pdsp_db_w_ptr->d_task_pm_gprs = meas_position; |
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diff
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|
1496 } |
3a2c43579200
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15
diff
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|
1497 |
3a2c43579200
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15
diff
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|
1498 /*-------------------------------------------------------*/ |
3a2c43579200
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15
diff
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|
1499 /* l1pddsp_meas_ctrl() */ |
3a2c43579200
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diff
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|
1500 /*-------------------------------------------------------*/ |
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15
diff
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|
1501 /* Parameters : */ |
3a2c43579200
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15
diff
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|
1502 /* Return : */ |
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15
diff
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|
1503 /* Functionality : */ |
3a2c43579200
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15
diff
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|
1504 /*-------------------------------------------------------*/ |
3a2c43579200
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15
diff
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|
1505 void l1pddsp_meas_ctrl(UWORD8 nbmeas, UWORD8 pm_pos) |
3a2c43579200
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15
diff
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|
1506 { |
3a2c43579200
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15
diff
changeset
|
1507 // Request Signal level measurement task to DSP. A bit map is passed |
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15
diff
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|
1508 // to DSP in order to specify the position of the measurement. |
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15
diff
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|
1509 // Note: MSB is TN = 0 and LSB is TN = 7. |
3a2c43579200
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15
diff
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|
1510 // Rem: swap I/Q is not managed for power measurements. |
3a2c43579200
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15
diff
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|
1511 // Note: currently a maximum of four Pm can be performed / TDMA. This would |
3a2c43579200
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15
diff
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|
1512 // be modified in a near futur. |
3a2c43579200
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15
diff
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|
1513 // Note: If a Rx is programmed i.e. pm_pos = 1, only a maximum |
3a2c43579200
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15
diff
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|
1514 // of 3 Pm is requested to DSP and position of the Pm are right shifted (Rx on TN = 0). |
3a2c43579200
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15
diff
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|
1515 // Remark: In packet Idle mode Rx are still on TN = 0. This implies three Pm |
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15
diff
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|
1516 // always after the Rx. |
3a2c43579200
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15
diff
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|
1517 l1ps_dsp_com.pdsp_db_w_ptr->d_task_pm_gprs = ((UWORD8) (0xff << (8 - nbmeas))) >> pm_pos; |
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15
diff
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|
1518 } |
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15
diff
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|
1519 |
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diff
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|
1520 /*-------------------------------------------------------*/ |
3a2c43579200
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15
diff
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|
1521 /* l1pddsp_meas_read() */ |
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15
diff
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|
1522 /*-------------------------------------------------------*/ |
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diff
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|
1523 /* Parameters : */ |
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15
diff
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|
1524 /* Return : */ |
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15
diff
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|
1525 /* Functionality : */ |
3a2c43579200
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15
diff
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|
1526 /*-------------------------------------------------------*/ |
3a2c43579200
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15
diff
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|
1527 void l1pddsp_meas_read(UWORD8 nbmeas, UWORD16 *a_pm) |
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15
diff
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|
1528 { |
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15
diff
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|
1529 UWORD8 i = 0; |
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15
diff
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|
1530 UWORD8 j; |
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15
diff
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|
1531 UWORD8 bit_mask = 0x80; |
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15
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|
1532 |
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15
diff
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|
1533 // Looks for first PM position |
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15
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|
1534 while ((i < 8) && (l1ps_dsp_com.pdsp_db_r_ptr->d_task_pm_gprs & bit_mask) == 0) |
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15
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|
1535 { |
3a2c43579200
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diff
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|
1536 i++; |
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15
diff
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|
1537 bit_mask >>= 1; |
3a2c43579200
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|
1538 } |
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diff
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|
1539 |
3a2c43579200
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diff
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|
1540 // Read 'nbmeas' contiguous PM levels from the first PM position |
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15
diff
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|
1541 // Note: PM are always programmed on contiguous timeslots |
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15
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|
1542 for (j = 0; ((j < nbmeas)&&(i < 8)); j++) |
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|
1543 { |
3a2c43579200
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15
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|
1544 // Download PM from DSP/MCU memory interface |
3a2c43579200
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|
1545 a_pm[j] = ((l1ps_dsp_com.pdsp_db_r_ptr->a_burst_pm_gprs[i] & 0xffff)); |
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|
1546 |
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|
1547 // Read next PM on following TN |
3a2c43579200
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|
1548 i++; |
3a2c43579200
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|
1549 } |
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|
1550 } |
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|
1551 |
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|
1552 /*-------------------------------------------------------*/ |
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|
1553 /* l1pddsp_load_bcchn_task() */ |
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|
1554 /*-------------------------------------------------------*/ |
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|
1555 /* Parameters : */ |
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|
1556 /* Return : */ |
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diff
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|
1557 /* Functionality : */ |
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|
1558 /*-------------------------------------------------------*/ |
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|
1559 void l1pddsp_load_bcchn_task(UWORD8 tsq,UWORD16 radio_freq ) |
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|
1560 { |
3a2c43579200
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|
1561 UWORD16 swap_bit = l1ps_swap_iq_dl(radio_freq); |
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|
1562 |
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diff
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|
1563 l1s_dsp_com.dsp_db_w_ptr->d_task_md = NBN_DSP_TASK | (swap_bit << 15); // Load BCCHN task |
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diff
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|
1564 l1s_dsp_com.dsp_db_w_ptr->d_ctrl_system |= tsq << B_TSQ; |
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|
1565 } |
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|
1566 #endif |