FreeCalypso > hg > tcs211-l1-reconst

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README update for the successful completion of the L1 reconstruction project
author Mychaela Falconia <falcon@freecalypso.org>
date Mon, 30 Oct 2017 18:03:24 +0000
parents bc7ca94e52e7
children
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
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283
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1 Objects in l1_ext.lib:
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2
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3 l1_afunc.obj: not exact, see explanation below
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Mychaela Falconia <falcon@freecalypso.org>
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4 l1_async.obj: perfect match
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Mychaela Falconia <falcon@freecalypso.org>
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5 l1_cmplx.obj: perfect match to 20070608 version except line number points
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Mychaela Falconia <falcon@freecalypso.org>
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6 l1_init.obj: perfect match
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Mychaela Falconia <falcon@freecalypso.org>
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7 l1_pwmgr.obj: perfect match
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Mychaela Falconia <falcon@freecalypso.org>
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8 l1_small.obj: perfect match
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9 l1_sync.obj: not exact, see explanation below
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10 l1_trace.obj: bits match perfectly, diff only in symbolic metadata
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11
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12 l1_dyn_dwl_afunc.obj: perfect match
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Mychaela Falconia <falcon@freecalypso.org>
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13 l1_dyn_dwl_apihisr.obj: perfect match
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Mychaela Falconia <falcon@freecalypso.org>
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14 l1_dyn_dwl_async.obj: perfect match
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15 l1_dyn_dwl_func.obj: not exact, see explanation below
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16 l1_dyn_dwl_init.obj: sole diff is in the num_of_primitives oddity,
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17 see explanation below
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18 l1_dyn_dwl_sync.obj: perfect match
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Mychaela Falconia <falcon@freecalypso.org>
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19
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Mychaela Falconia <falcon@freecalypso.org>
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20 l1audio_abb.obj: perfect match
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Mychaela Falconia <falcon@freecalypso.org>
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21 l1audio_afunc.obj: bits match perfectly, diff only in symbolic metadata
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22 l1audio_async.obj: diffs only in register alloc and symbolic metadata
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23 l1audio_back.obj: perfect match
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24 l1audio_drive.obj: perfect match
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25 l1audio_init.obj: perfect match
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26
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27 l1p_afun.obj: perfect match
7ad882cbce4c STATUS: updated for l1p_* deblobbing
Mychaela Falconia <falcon@freecalypso.org>
parents: 289
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28 l1p_asyn.obj: perfect match
7ad882cbce4c STATUS: updated for l1p_* deblobbing
Mychaela Falconia <falcon@freecalypso.org>
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29 l1p_cmpl.obj: perfect match to 20070608 version
7ad882cbce4c STATUS: updated for l1p_* deblobbing
Mychaela Falconia <falcon@freecalypso.org>
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30 l1p_sync.obj: perfect match
7ad882cbce4c STATUS: updated for l1p_* deblobbing
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31
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32 l1tm_async.obj: bits match perfectly, diff only in the line number points
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33 l1tm_func.obj: bits match perfectly, diffs only in symbolic and line numbers
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34 l1tm_stats.obj: perfect match
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35
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36 Objects in l1_int.lib:
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37
288
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38 dl1_com.obj: not exact, see analysis below
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39 l1_api_hisr.obj: perfect match
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Mychaela Falconia <falcon@freecalypso.org>
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40 l1_cmplx_intram.obj: perfect match to 20070608 version
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Mychaela Falconia <falcon@freecalypso.org>
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41 l1_ctl.obj: perfect match to 20070608 version
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Mychaela Falconia <falcon@freecalypso.org>
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42 l1_drive.obj: perfect match
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Mychaela Falconia <falcon@freecalypso.org>
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43 l1_func.obj: perfect match
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Mychaela Falconia <falcon@freecalypso.org>
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44 l1_mfmgr.obj: perfect match
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45 l1_sync_intram.obj: not exact, see explanation below
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46
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47 l1audio_func.obj: perfect match
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Mychaela Falconia <falcon@freecalypso.org>
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48 l1audio_sync.obj: perfect match
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Mychaela Falconia <falcon@freecalypso.org>
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49
336
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50 l1p_cmpl_intram.obj: perfect match
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51 l1p_ctl.obj: perfect match
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bc7ca94e52e7 STATUS: l1p_driv.obj reconstruction is now perfect
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52 l1p_driv.obj: perfect match
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53 l1p_func.obj: perfect match
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54 l1p_sync_intram.obj: perfect match
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01b78eaf67e2 STATUS: macs.obj is a perfect match
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55 macs.obj: perfect match
336
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56
283
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57 Objects in l1_custom_ext.lib:
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58
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Mychaela Falconia <falcon@freecalypso.org>
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59 l1audio_cust.obj: dead functions not reconstructed, perfect match
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Mychaela Falconia <falcon@freecalypso.org>
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60 otherwise
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Mychaela Falconia <falcon@freecalypso.org>
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61 l1tm_cust.obj: perfect match
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Mychaela Falconia <falcon@freecalypso.org>
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62 l1tm_tpu12.obj: perfect match
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63
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64 Objects in l1_custom_int.lib:
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65
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66 ind_os.obj: perfect match
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67 l1_cust.obj: perfect match
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Mychaela Falconia <falcon@freecalypso.org>
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68
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Mychaela Falconia <falcon@freecalypso.org>
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69 Objects in tpudrv.lib:
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70
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ba47d35a72f3 STATUS: p_tpudr12.obj is a perfect match
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71 p_tpudr12.obj: perfect match
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72 tpudrv.obj: perfect match
288
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73 tpudrv12.obj: not exact, see analysis below
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74
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75 Detailed analysis of differences, i.e., cases where the reconstructed C code
33b35965b4a0 STATUS: began analysis of the differences in the non-exact objects
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76 compiles into an object that is not bit-identical to the original blob:
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77
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78 l1_afunc.obj:
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79
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80 The l1_afunc.c module from LoCosto is used without any changes:
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81 it compiled right away after adding one constant to l1_const.h,
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82 and the result of recompilation is identical to the original up until
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83 the l1a_clip_txpwr() function, which is the last function in the module.
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84
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85 Disassembly of the original blob version of this function has been
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86 analyzed and found to be identical in logic to the available C code,
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87 but there must have been some change to the code expression that
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88 results in different output from the compiler. In particular, the
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89 symbolic info indicates the presence of a local variable named power
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90 in the original, but no such local var exists in the LoCosto version.
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91 The TSM30 version was of no help as it is entirely different there.
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92
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93 See g23m/objdiff/l1_ext/l1_afunc.notes for further info.
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94
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95 l1_sync.obj:
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96
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97 The last function in this module is l1s_dedicated_mode_manager();
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98 the two preceding functions match perfectly, but for this last function
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99 when the reconstructed code is recompiled, the compiler's register
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Mychaela Falconia <falcon@freecalypso.org>
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100 allocator makes different picks for reasons that could not be
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Mychaela Falconia <falcon@freecalypso.org>
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101 successfully reversed. Because the code is compiled in Thumb mode
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Mychaela Falconia <falcon@freecalypso.org>
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102 and the compiler made a different choice between low and high registers
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103 in some places, the instructions do not line perfectly. The logic match
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104 has instead been verified by manual comparison.
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105
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Mychaela Falconia <falcon@freecalypso.org>
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106 l1_sync_intram.obj:
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107
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108 Similar situation in the l1s_schedule_tasks() function: the function
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109 is huge, there is an unknown set of factors determining what the
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110 compiler's register allocator will do, and in this case there is even
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Mychaela Falconia <falcon@freecalypso.org>
parents: 288
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111 a difference in the choice of register vs. stack for some temporaries.
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112 As a result, the code does not line up and the logic had to be verified
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Mychaela Falconia <falcon@freecalypso.org>
parents: 288
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113 manually. All other functions (preceding and following) match
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Mychaela Falconia <falcon@freecalypso.org>
parents: 288
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114 perfectly.
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115
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116 dl1_com.obj:
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117
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118 The reconstruction of this module is not exact, but the logic has
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Mychaela Falconia <falcon@freecalypso.org>
parents: 284
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119 been verified to be an exact match except for the removal of some
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120 non-functional bogons. Specifically:
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121
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122 l1_create_ISR(): diff in one local variable name (result vs. status),
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parents: 284
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123 affects the generated assert string, but the length stays the same.
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parents: 284
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124 This assert string also contains the line number which differs
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Mychaela Falconia <falcon@freecalypso.org>
parents: 284
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125 (3 digits in both cases), and the location of the string changes
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Mychaela Falconia <falcon@freecalypso.org>
parents: 284
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126 because of the diffs in later functions listed below.
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Mychaela Falconia <falcon@freecalypso.org>
parents: 284
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127 Verified exact match otherwise.
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Mychaela Falconia <falcon@freecalypso.org>
parents: 284
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128
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Mychaela Falconia <falcon@freecalypso.org>
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129 TP_FrameIntHandler(): verified exact match.
4d9af8de3973 STATUS: dl1_com differences analyzed and documented
Mychaela Falconia <falcon@freecalypso.org>
parents: 284
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130
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Mychaela Falconia <falcon@freecalypso.org>
parents: 284
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131 layer_1_sync_HISR_entry(): the version in the blob contains a
4d9af8de3973 STATUS: dl1_com differences analyzed and documented
Mychaela Falconia <falcon@freecalypso.org>
parents: 284
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132 non-functional bogon which has not been reconstructed, see the
4d9af8de3973 STATUS: dl1_com differences analyzed and documented
Mychaela Falconia <falcon@freecalypso.org>
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133 comments in the reconstructed source. Verified to be an exact match
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134 except for the removal of this bogon.
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135
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136 rx_tch_data(): empty function in both versions, trivial exact match.
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diff changeset
137
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138 tx_tch_data(): this stub function is supposed to return a pointer,
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139 but the original blob does a bare bx lr, returning whatever happens to
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140 be in r0 on entry, which is unpredictable as the function takes no
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141 arguments. The reconstructed version returns NULL.
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142
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143 Strings and literals after the functions: manually verified to be an
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144 exact match.
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145
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146 .bss section: the original blob contains these defunct uninitialized
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147 data objects: BACK_queue, DLL1_queue, L1C1_queue, RRM1_queue, pool_52,
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148 pool_100, pool_400, pool_1600, and a static variable i in
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149 layer_1_sync_HISR_entry() related to the bogon mentioned above. These
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diff changeset
150 global data objects are not referenced from anywhere else in the
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151 firmware and the link succeeds without them being present, hence they
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152 have been omitted from the reconstruction. The rest is an exact match.
284
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153
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154 l1_dyn_dwl_func.obj:
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155
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156 The LoCosto version uses a function (implemented in l1_func.c in
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157 the LoCosto code) named l1_memcpy_16bit() to download patch bits
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158 into the DSP's API RAM; the function does what the name says, and
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159 the logic of using 16-bit accesses when hitting this API RAM makes
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160 perfect sense to me (Mychaela). The original TCS211 code apparently
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161 used plain memcpy(), which the compiler turned into its C$MEMCPY call.
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162
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163 If one does a #define l1_memcpy_16bit memcpy in l1_dyn_dwl_func.c,
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164 the resulting l1_dyn_dwl_func.obj is almost bit-identical to the
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165 original blob: the only diff is in register allocation - the compiler's
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166 register allocator picks a different choice of registers, but all
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diff changeset
167 instructions still perfectly line up.
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168
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diff changeset
169 For production use of our reconstructed TCS211 L1 code, we have adopted
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diff changeset
170 the version with l1_memcpy_16bit() - the function body itself has been
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171 moved into l1_dyn_dwl_func.c so that l1_func.c remains a perfect match.
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diff changeset
172
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173 l1_dyn_dwl_init.obj:
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174
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175 In the TCS211 configuration without L1_GTT, there are a total of 5
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176 signals (aka primitives aka L1 messages) which trigger a dynamic
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177 DSP patch download. These 5 signals are enumerated in
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178 signal_patch_array[] in l1_dyn_dwl_afunc.c (which has been reconstructed
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diff changeset
179 to a perfect match), and their total count (which should be 5) goes into
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180 l1a.dyn_dwnld.num_of_primitives, set in l1_dyn_dwnld_initialize_var() in
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181 l1_dyn_dwl_init.c.
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182
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183 In the original blob version this num_of_primitives variable ends up
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184 being set to 6: first set to 2, then incremented by 4. In the LoCosto
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diff changeset
185 source this var is first set to 0 as they apparently have no patches
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186 that are independent of compilation config options, and then incremented
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187 for every enabled option.
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188
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189 In our reconstruction we have made the GPRS and AMR_SCH patches and the
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190 primitives that trigger them mandatory, and conditionalized the E2 and
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191 AMR_MMS patches on MELODY_E2. The GPRS and AMR_MMS critters are
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192 preinstalled by the static patch, and get pushed out by AMR_SCH and E2,
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193 respectively. Of the 5 primitives listed in signal_patch_array[] in
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diff changeset
194 the original blob, the first 2 are always-present core ones, whereas
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195 the last 3 are specific to E2. The AMR_MMS patch is reinstated upon
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diff changeset
196 L1_BACK_MELODY_E2_UNLOAD_INSTRUMENT_CON.
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197
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198 Based on the above reasoning, our reconstructed version sets
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199 l1a.dyn_dwnld.num_of_primitives to 5 in the full configuration: first
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200 sets to 2, then increments by 3. If one makes a sans-MELODY_E2 build,
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diff changeset
201 only the GPRS and AMR_SCH patches will be retained, and only the two
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diff changeset
202 non-E2 primitives for entry into and exit from dedicated mode.
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diff changeset
203
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204 l1audio_async.obj:
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diff changeset
205
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diff changeset
206 The only bit diff is in register allocation - the compiler's register
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207 allocator picks a different choice of registers, but all instructions
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diff changeset
208 still perfectly line up. There is also a slight diff in the symbolic
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diff changeset
209 metadata emitted for functions, which might be related to the diff in
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diff changeset
210 the register allocation.
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diff changeset
211
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diff changeset
212 The root cause of these diffs could not be found, but there is no
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diff changeset
213 functional difference as only some in-function temporary registers
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diff changeset
214 have been interchanged.
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diff changeset
215
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216 l1audio_cust.obj:
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diff changeset
217
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218 The original blob version has these demo/test functions at the end of
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diff changeset
219 the module:
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diff changeset
220
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221 audio_melo_e1_demo1_start()
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222 audio_melo_e1_demo1_stop()
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223 audio_melo_e1_demo2_start()
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diff changeset
224 audio_melo_e1_demo2_stop()
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diff changeset
225 audio_melo_e2_load_lsi()
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diff changeset
226 audio_melo_e2_demo1_start()
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diff changeset
227 audio_melo_e2_demo1_stop()
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diff changeset
228 audio_melo_e2_demo2_start()
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229 audio_melo_e2_demo2_stop()
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diff changeset
230
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diff changeset
231 These functions are dead code, i.e., they are not called or referenced
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diff changeset
232 from anywhere else in the firmware, and the link succeeds without them
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diff changeset
233 being present. These dead functions have been omitted from the
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diff changeset
234 reconstructed version. The reconstruction is a perfect match otherwise.
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diff changeset
235
288
595cdc5ff4e5 tpudrv12 differences analyzed and documented
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diff changeset
236 tpudrv12.obj:
595cdc5ff4e5 tpudrv12 differences analyzed and documented
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diff changeset
237
595cdc5ff4e5 tpudrv12 differences analyzed and documented
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diff changeset
238 The reconstruction of this module was more of a translation of logic
595cdc5ff4e5 tpudrv12 differences analyzed and documented
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diff changeset
239 from disassembly to C than adaptation of source from other versions,
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diff changeset
240 hence it is not a bit-for-bit match or even close. However, the logic
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diff changeset
241 has been carefully verified and confirmed to match the original; see
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parents: 285
diff changeset
242 chipsetsw/layer1/tpu_drivers/source0/tpudrv12.notes for the details.