annotate ueda/sverp/main.c @ 45:3bdb1b5ff3d0

pads2gpcb: gpcb dimension output implemented
author Mychaela Falconia <falcon@ivan.Harhan.ORG>
date Sat, 30 Jan 2016 07:15:31 +0000
parents 7b4f78fcca08
children
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1 /*
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2 * main() function for ueda-sverp
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3 */
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4
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5 #include <stdio.h>
4
7b4f78fcca08 ueda/sverp Linuxified
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6 #include <stdlib.h>
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7 #include <unistd.h>
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8 #include "struct.h"
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9
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10 struct module_def *glob_module_list, *top_module_def;
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11 char *primitives_filename = "primitives", *top_module_expl;
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12 int verbose, top_module_candidates;
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13 char *output_filename = "sverp.out";
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14
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15 static void
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16 usage()
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17 {
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18 fprintf(stderr,
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19 "usage: ueda-sverp [-p primfile] [-t top-module] [-v] verilog-sources\n");
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20 exit(1);
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21 }
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22
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23 static void
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24 process_options(argc, argv)
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25 char **argv;
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26 {
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27 register int c;
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28
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29 while ((c = getopt(argc, argv, "I:o:p:t:v")) != EOF) {
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30 switch (c) {
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31 case 'I':
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32 add_symfile_dir(optarg);
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33 continue;
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34 case 'o':
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35 output_filename = optarg;
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36 continue;
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37 case 'p':
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38 primitives_filename = optarg;
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39 continue;
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40 case 't':
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41 top_module_expl = optarg;
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42 continue;
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43 case 'v':
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44 verbose++;
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45 continue;
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46 default:
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47 usage();
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48 }
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49 }
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50 }
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51
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52 main(argc, argv)
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53 char **argv;
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54 {
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55 extern int optind;
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56
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57 process_options(argc, argv);
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58 if (optind >= argc)
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59 usage();
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60 for (; optind < argc; optind++) {
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61 if (verbose)
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62 printf("Reading Verilog source %s\n", argv[optind]);
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63 read_verilog_file(argv[optind]);
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64 }
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65 if (top_module_expl)
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66 process_explicit_topmod();
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67 if (verbose)
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68 printf("Reading primitive definitions from %s\n",
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69 primitives_filename);
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70 set_default_sympath(); /* for xGA definition files */
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71 read_primitives_file(primitives_filename);
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72 if (verbose)
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73 printf("Linking instantiations to lower modules\n");
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74 link_pass();
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75 if (!top_module_def) {
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76 fprintf(stderr, "error: no top module found\n");
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77 exit(1);
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78 }
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79 if (!top_module_expl && top_module_candidates > 1) {
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80 fprintf(stderr,
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81 "error: more than one top module candidate, use -t option\n");
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82 exit(1);
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83 }
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84 if (verbose)
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85 printf("Elaborating hierarchy from top module %s\n",
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86 top_module_def->name);
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87 elaborate_module(top_module_def, top_module_def->name, "", 0);
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88 tally_output_nets();
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89 generate_output();
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90 exit(0);
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91 }