FreeCalypso > hg > fc-pcm-if

annotate fpga/tools/yosys-tee @ 5:3ae4a6ca5639

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add README
author Mychaela Falconia <falcon@freecalypso.org>
date Sat, 12 Oct 2024 03:11:17 +0000
parents 4624f3da093a
children
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4624f3da093a starting project with FPGA infra from fc-sim-sniff
Mychaela Falconia <falcon@freecalypso.org>
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1 #!/bin/sh
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2
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3 if [ $# -lt 4 ]
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Mychaela Falconia <falcon@freecalypso.org>
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4 then
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Mychaela Falconia <falcon@freecalypso.org>
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5 echo "usage: $0 top-module json-output report-out verilog-src..." 1>&2
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6 exit 1
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7 fi
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8
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9 top="$1"
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10 json="$2"
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11 report="$3"
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12
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13 shift
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14 shift
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15 shift
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16
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17 rm -f "$json"
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18 yosys -p "synth_ice40 -top $top -json $json" "$@" | tee "$report"
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19
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20 if [ -f "$json" ]
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21 then
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22 echo "$json created, declaring success"
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23 exit 0
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24 else
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25 echo "$json NOT created, declaring error"
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26 exit 1
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27 fi