FreeCalypso > hg > fc-pcm-if
annotate fpga/tools/yosys-wrap @ 11:e93a11f44e6f
fc-mcsi-rxtx: implement basic Tx
author | Mychaela Falconia <falcon@freecalypso.org> |
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date | Mon, 28 Oct 2024 06:34:42 +0000 |
parents | 4624f3da093a |
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4624f3da093a
starting project with FPGA infra from fc-sim-sniff
Mychaela Falconia <falcon@freecalypso.org>
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1 #!/bin/sh |
4624f3da093a
starting project with FPGA infra from fc-sim-sniff
Mychaela Falconia <falcon@freecalypso.org>
parents:
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2 |
4624f3da093a
starting project with FPGA infra from fc-sim-sniff
Mychaela Falconia <falcon@freecalypso.org>
parents:
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3 if [ $# -lt 3 ] |
4624f3da093a
starting project with FPGA infra from fc-sim-sniff
Mychaela Falconia <falcon@freecalypso.org>
parents:
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4 then |
4624f3da093a
starting project with FPGA infra from fc-sim-sniff
Mychaela Falconia <falcon@freecalypso.org>
parents:
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5 echo "usage: $0 top-module json-output verilog-src..." 1>&2 |
4624f3da093a
starting project with FPGA infra from fc-sim-sniff
Mychaela Falconia <falcon@freecalypso.org>
parents:
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6 exit 1 |
4624f3da093a
starting project with FPGA infra from fc-sim-sniff
Mychaela Falconia <falcon@freecalypso.org>
parents:
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7 fi |
4624f3da093a
starting project with FPGA infra from fc-sim-sniff
Mychaela Falconia <falcon@freecalypso.org>
parents:
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8 |
4624f3da093a
starting project with FPGA infra from fc-sim-sniff
Mychaela Falconia <falcon@freecalypso.org>
parents:
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9 top="$1" |
4624f3da093a
starting project with FPGA infra from fc-sim-sniff
Mychaela Falconia <falcon@freecalypso.org>
parents:
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10 json="$2" |
4624f3da093a
starting project with FPGA infra from fc-sim-sniff
Mychaela Falconia <falcon@freecalypso.org>
parents:
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11 |
4624f3da093a
starting project with FPGA infra from fc-sim-sniff
Mychaela Falconia <falcon@freecalypso.org>
parents:
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12 shift |
4624f3da093a
starting project with FPGA infra from fc-sim-sniff
Mychaela Falconia <falcon@freecalypso.org>
parents:
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13 shift |
4624f3da093a
starting project with FPGA infra from fc-sim-sniff
Mychaela Falconia <falcon@freecalypso.org>
parents:
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14 |
4624f3da093a
starting project with FPGA infra from fc-sim-sniff
Mychaela Falconia <falcon@freecalypso.org>
parents:
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15 rm -f "$json" |
4624f3da093a
starting project with FPGA infra from fc-sim-sniff
Mychaela Falconia <falcon@freecalypso.org>
parents:
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16 yosys -p "synth_ice40 -top $top -json $json" "$@" |
4624f3da093a
starting project with FPGA infra from fc-sim-sniff
Mychaela Falconia <falcon@freecalypso.org>
parents:
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17 |
4624f3da093a
starting project with FPGA infra from fc-sim-sniff
Mychaela Falconia <falcon@freecalypso.org>
parents:
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18 if [ -f "$json" ] |
4624f3da093a
starting project with FPGA infra from fc-sim-sniff
Mychaela Falconia <falcon@freecalypso.org>
parents:
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19 then |
4624f3da093a
starting project with FPGA infra from fc-sim-sniff
Mychaela Falconia <falcon@freecalypso.org>
parents:
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20 echo "$json created, declaring success" |
4624f3da093a
starting project with FPGA infra from fc-sim-sniff
Mychaela Falconia <falcon@freecalypso.org>
parents:
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21 exit 0 |
4624f3da093a
starting project with FPGA infra from fc-sim-sniff
Mychaela Falconia <falcon@freecalypso.org>
parents:
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22 else |
4624f3da093a
starting project with FPGA infra from fc-sim-sniff
Mychaela Falconia <falcon@freecalypso.org>
parents:
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23 echo "$json NOT created, declaring error" |
4624f3da093a
starting project with FPGA infra from fc-sim-sniff
Mychaela Falconia <falcon@freecalypso.org>
parents:
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24 exit 1 |
4624f3da093a
starting project with FPGA infra from fc-sim-sniff
Mychaela Falconia <falcon@freecalypso.org>
parents:
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25 fi |