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annotate src/cs/drivers/drv_app/ffs/board/intelsbdrv.c @ 46:559a8b3ef10b

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FFS code: first attempt at non-invasive gcc support
author Mychaela Falconia <falcon@freecalypso.org>
date Thu, 19 Jul 2018 00:35:33 +0000
parents b6a5e36de839
children 4484ab3f6ab3
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
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1 /******************************************************************************
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2 * Flash File System (ffs)
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3 * Idea, design and coding by Mads Meisner-Jensen, mmj@ti.com
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4 *
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5 * FFS AMD single bank low level flash driver RAM code
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6 *
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7 * $Id: intelsbdrv.c 1.13 Thu, 08 Jan 2004 15:05:23 +0100 tsj $
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8 *
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9 ******************************************************************************/
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10
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11 #include "ffs.cfg"
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12
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13 #include "ffs/ffs.h"
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14 #include "ffs/board/drv.h"
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15 #include "ffs/board/ffstrace.h"
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16 #include "nucleus.h"
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17
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18
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19 #define INTEL_UNLOCK_SLOW 1
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20
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21
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22 #undef tlw
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23 #define tlw(contents)
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24 #undef ttw
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25 #define ttw(contents)
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26
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27 // Status bits for Intel flash memory devices
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28 #define INTEL_STATE_MACHINE_DONE (1<<7)
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29 #define FLASH_READ(addr) (*(volatile uint16 *) (addr))
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30 #define FLASH_WRITE(addr, data) (*(volatile uint16 *) (addr)) = data
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31
46
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32 #ifdef __GNUC__
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33 asm(".globl ffsdrv_ram_intel_begin");
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34 asm("ffsdrv_ram_intel_begin:");
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35 #else
0
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36 asm(" .label _ffsdrv_ram_intel_begin");
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37 asm(" .def _ffsdrv_ram_intel_begin");
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38 #endif
0
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39
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40 uint32 intel_int_disable(void);
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41 void intel_int_enable(uint32 tmp);
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42
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43 /******************************************************************************
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44 * INTEL Single Bank Driver Functions
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45 ******************************************************************************/
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46 // Actually we should have disabled and enable the interrupts in this
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47 // function, but when the interrupt functions are used Target don't run!
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48 // Anyway, currently the interrupts are already disabled at this point thus
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49 // it does not cause any problems.
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50 int ffsdrv_ram_intel_sb_init(void)
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51 {
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52 uint32 cpsr, i;
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53 volatile char *addr;
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54 uint16 status;
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55
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56 for (i = 0; i < dev.numblocks; i++)
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57 {
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58 addr = block2addr(i);
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59
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60 *addr = 0x50; // Intel Clear Status Register
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61 *addr = 0xFF; // Intel read array
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62
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63 *addr = 0x60; // Intel Config Setup
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64 *addr = 0xD0; // Intel Unlock Block
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65
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66 // Wait for unlock to finish
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67 do {
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68 status = FLASH_READ(addr);
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69 } while (!(status & INTEL_STATE_MACHINE_DONE));
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70
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71 *addr = 0x70; // Intel Read Status Register
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72 status = FLASH_READ(addr);
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73
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74 // Is there an erase suspended?
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75 if ((status & 0x40) != 0) {
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76 *addr = 0xD0; // Intel erase resume
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77
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78 *addr = 0x70; // Intel Read Status Register
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79 // wait for erase to finish
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80 do {
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81 status = FLASH_READ(addr);
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82 } while (!(status & INTEL_STATE_MACHINE_DONE));
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83 }
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84
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85 *addr = 0xFF; // Intel Read Array
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86 }
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87
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88 return 0;
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89 }
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90
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91 void ffsdrv_ram_intel_sb_write_halfword(volatile uint16 *addr, uint16 value)
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92 {
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93 uint32 cpsr;
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94
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95 ttw(ttr(TTrDrv, "wh(%x,%x)" NL, addr, value));
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96
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97 if (~*addr & value) {
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98 ttw(ttr(TTrFatal, "wh(%x,%x->%x) fatal" NL, addr, *addr, value));
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99 return;
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100 }
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101
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102 cpsr = intel_int_disable();
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103 tlw(led_on(LED_WRITE));
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104
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105 #if (INTEL_UNLOCK_SLOW == 1)
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106 *addr = 0x60; // Intel Config Setup
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107 *addr = 0xD0; // Intel Unlock Block
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108 #endif
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109
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110 *addr = 0x50; // Intel Clear Status Register
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111 *addr = 0x40; // Intel program byte/word
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112 *addr = value;
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113 while ((*addr & 0x80) == 0)
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114 ;
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115 *addr = 0xFF; // Intel read array
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116 tlw(led_off(LED_WRITE));
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117 intel_int_enable(cpsr);
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118 }
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119
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120 void ffsdrv_ram_intel_sb_erase(uint8 block)
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121 {
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122 volatile char *addr;
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123 uint32 cpsr;
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124 uint16 poll;
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125
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126 ttw(ttr(TTrDrvEra, "e(%d)" NL, block));
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127
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128 addr = block2addr(block);
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129
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130 cpsr = intel_int_disable();
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131 tlw(led_on(LED_ERASE));
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132
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133 #if (INTEL_UNLOCK_SLOW == 1)
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134 *addr = 0x60; // Intel Config Setup
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Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
135 *addr = 0xD0; // Intel Unlock Block
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
136 #endif
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
137
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
138 *addr = 0x50; // Intel Clear Status Register
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
139 *addr = 0x20; // Intel Erase Setup
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
140 *addr = 0xD0; // Intel Erase Confirm
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
141 *addr = 0x70; // Intel Read Status Register
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
142
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
143 // Wait for erase to finish.
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
144 while ((*addr & 0x80) == 0) {
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
145 tlw(led_toggle(LED_ERASE));
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
146 // Poll interrupts, taking interrupt mask into account.
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
147 if (INT_REQUESTED)
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
148 {
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
149 // 1. suspend erase
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
150 // 2. enable interrupts
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
151 // .. now the interrupt code executes
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
152 // 3. disable interrupts
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
153 // 4. resume erase
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
154
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
155 tlw(led_on(LED_ERASE_SUSPEND));
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
156
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
157 *addr = 0xB0; // Intel Erase Suspend
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
158 *addr = 0x70; // Intel Read Status Register
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
159 while (((poll = *addr) & 0x80) == 0)
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
160 ;
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
161
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
162 // If erase is complete, exit immediately
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
163 if ((poll & 0x40) == 0)
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
164 break;
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
165
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
166 *addr = 0xFF; // Intel read array
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
167
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
168 tlw(led_off(LED_ERASE_SUSPEND));
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
169 intel_int_enable(cpsr);
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
170
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
171 // Other interrupts and tasks run now...
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
172
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
173 cpsr = intel_int_disable();
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
174 tlw(led_on(LED_ERASE_SUSPEND));
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
175
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
176 *addr = 0xD0; // Intel erase resume
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
177 // The following "extra" Read Status command is required because Intel has
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
178 // changed the specification of the W30 flash! (See "1.8 Volt Intel®
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
179 // Wireless Flash Memory with 3 Volt I/O 28F6408W30, 28F640W30, 28F320W30
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
180 // Specification Update")
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
181 *addr = 0x70; // Intel Read Status Register
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
182
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
183 tlw(led_off(LED_ERASE_SUSPEND));
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
184 }
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
185 }
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
186 *addr = 0xFF; // Intel read array
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
187
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
188 tlw(led_on(LED_ERASE));
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
189 tlw(led_off(LED_ERASE));
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
190 intel_int_enable(cpsr);
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
191 }
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
192
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
193 // TODO: remove below function, not in use anymore.
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
194 void ffsdrv_ram_intel_erase(uint8 block)
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
195 {
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
196 uint32 cpsr;
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
197 uint16 status;
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
198
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
199 ttw(ttr(TTrDrvErase, "e(%d)" NL, block));
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
200 tlw(led_on(LED_ERASE));
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
201
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
202 dev.addr = (uint16 *) block2addr(block);
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
203
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
204 cpsr = intel_int_disable();
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
205 dev.state = DEV_ERASE;
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
206
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
207 *dev.addr = 0x60; // Intel Config setup
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
208 *dev.addr = 0xD0; // Intel Unlock block
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
209
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
210 *dev.addr = 0x50; // Intel clear status register (not really necessary)
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
211 *dev.addr = 0x20; // Intel erase setup
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
212 *dev.addr = 0xD0; // Intel erase confirm
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
213
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
214 intel_int_enable(cpsr);
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
215
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
216 while ((*dev.addr & 0x80) == 0)
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
217 ;
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
218
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
219 *dev.addr = 0xFF; // Intel read array
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
220 dev.state = DEV_READ;
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
221 tlw(led_off(LED_WRITE));
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
222 }
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
223
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
224
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
225 /******************************************************************************
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
226 * Interrupt Enable/Disable
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
227 ******************************************************************************/
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
228
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
229 uint32 intel_int_disable(void)
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
230 {
46
559a8b3ef10b FFS code: first attempt at non-invasive gcc support
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
231 #ifdef __GNUC__
559a8b3ef10b FFS code: first attempt at non-invasive gcc support
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
232 return NU_Control_Interrupts(0xC0);
559a8b3ef10b FFS code: first attempt at non-invasive gcc support
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
233 #else
0
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
234 asm(" .state16");
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
235 asm(" mov A1, #0xC0");
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
236 asm(" ldr A2, tct_intel_disable");
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
237 asm(" bx A2 ");
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
238
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
239 asm("tct_intel_disable .field _TCT_Control_Interrupts+0,32");
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
240 asm(" .global _TCT_Control_Interrupts");
46
559a8b3ef10b FFS code: first attempt at non-invasive gcc support
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
241 #endif
0
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
242 }
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
243
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
244 void intel_int_enable(uint32 cpsr)
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
245 {
46
559a8b3ef10b FFS code: first attempt at non-invasive gcc support
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
246 #ifdef __GNUC__
559a8b3ef10b FFS code: first attempt at non-invasive gcc support
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
247 return NU_Control_Interrupts(cpsr);
559a8b3ef10b FFS code: first attempt at non-invasive gcc support
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
248 #else
0
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
249 asm(" .state16");
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
250 asm(" ldr A2, tct_intel_enable");
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
251 asm(" bx A2 ");
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
252
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
253 asm("tct_intel_enable .field _TCT_Control_Interrupts+0,32");
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
254 asm(" .global _TCT_Control_Interrupts");
46
559a8b3ef10b FFS code: first attempt at non-invasive gcc support
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
255 #endif
0
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
256 }
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
257
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
258 // Even though we have this end label, we cannot determine the number of
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
259 // constant/PC-relative data following the code!
46
559a8b3ef10b FFS code: first attempt at non-invasive gcc support
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
260 #ifdef __GNUC__
559a8b3ef10b FFS code: first attempt at non-invasive gcc support
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
261 asm(".globl ffsdrv_ram_intel_end");
559a8b3ef10b FFS code: first attempt at non-invasive gcc support
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
262 asm("ffsdrv_ram_intel_end:");
559a8b3ef10b FFS code: first attempt at non-invasive gcc support
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
263 #else
0
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
264 asm(" .state32");
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
265 asm(" .label _ffsdrv_ram_intel_end");
b6a5e36de839 src/cs: initial import from Magnetite
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
266 asm(" .def _ffsdrv_ram_intel_end");
46
559a8b3ef10b FFS code: first attempt at non-invasive gcc support
Mychaela Falconia <falcon@freecalypso.org>
parents: 0
diff changeset
267 #endif