FreeCalypso > hg > fc-sim-sniff

annotate sw/sniff-rx/mainloop.c @ 35:695ca51e1564

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doc/Sniffer-FPGA-design: update for finished work
author Mychaela Falconia <falcon@freecalypso.org>
date Wed, 30 Aug 2023 01:09:00 +0000
parents b112c2df6c43
children
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1 /*
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2 * This module holds our main loop code, factored out into a separate
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3 * function that is called from main() after initialization.
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4 */
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5
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6 #include <sys/types.h>
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7 #include <sys/time.h>
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8 #include <sys/errno.h>
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9 #include <stdio.h>
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10 #include <stdlib.h>
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11 #include <unistd.h>
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12
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13 extern int target_fd;
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14 extern FILE *main_outf;
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15
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16 struct timeval curtime;
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17
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18 main_loop()
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19 {
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20 fd_set fds;
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21 struct timeval tv;
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22 u_char buf[512];
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23 int cc, i, is_active;
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24
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25 for (is_active = 0; ; ) {
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26 FD_ZERO(&fds);
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27 FD_SET(target_fd, &fds);
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28 if (is_active) {
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29 tv.tv_sec = 1;
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30 tv.tv_usec = 0;
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31 cc = select(target_fd+1, &fds, 0, 0, &tv);
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32 } else
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33 cc = select(target_fd+1, &fds, 0, 0, 0);
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34 gettimeofday(&curtime, 0);
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35 if (cc < 0) {
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36 if (errno == EINTR)
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37 continue;
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38 perror("select");
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39 exit(1);
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40 }
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41 if (cc == 0) {
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42 is_active = 0;
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43 fflush(main_outf);
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44 flush_pending_byte();
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45 continue;
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46 }
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47 cc = read(target_fd, buf, sizeof buf);
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48 if (cc < 0) {
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49 perror("serial port read");
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50 exit(1);
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51 }
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52 if (cc == 0) {
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53 fprintf(stderr, "read EOF from serial port\n");
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54 exit(1);
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55 }
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56 current_date_time();
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57 for (i = 0; i < cc; i++)
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58 rx_byte_in(buf[i]);
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59 is_active = 1;
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60 }
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61 }