FreeCalypso > hg > fc-sim-sniff
view sw/sniff-rx/mainloop.c @ 35:695ca51e1564
doc/Sniffer-FPGA-design: update for finished work
author | Mychaela Falconia <falcon@freecalypso.org> |
---|---|
date | Wed, 30 Aug 2023 01:09:00 +0000 |
parents | b112c2df6c43 |
children |
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/* * This module holds our main loop code, factored out into a separate * function that is called from main() after initialization. */ #include <sys/types.h> #include <sys/time.h> #include <sys/errno.h> #include <stdio.h> #include <stdlib.h> #include <unistd.h> extern int target_fd; extern FILE *main_outf; struct timeval curtime; main_loop() { fd_set fds; struct timeval tv; u_char buf[512]; int cc, i, is_active; for (is_active = 0; ; ) { FD_ZERO(&fds); FD_SET(target_fd, &fds); if (is_active) { tv.tv_sec = 1; tv.tv_usec = 0; cc = select(target_fd+1, &fds, 0, 0, &tv); } else cc = select(target_fd+1, &fds, 0, 0, 0); gettimeofday(&curtime, 0); if (cc < 0) { if (errno == EINTR) continue; perror("select"); exit(1); } if (cc == 0) { is_active = 0; fflush(main_outf); flush_pending_byte(); continue; } cc = read(target_fd, buf, sizeof buf); if (cc < 0) { perror("serial port read"); exit(1); } if (cc == 0) { fprintf(stderr, "read EOF from serial port\n"); exit(1); } current_date_time(); for (i = 0; i < cc; i++) rx_byte_in(buf[i]); is_active = 1; } }