FreeCalypso > hg > fc-sim-sniff

annotate fpga/sniffer-pps/Makefile @ 53:737579209153

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fpga/sniffer-pps: add LED indication of running SIM CLK
author Mychaela Falconia <falcon@freecalypso.org>
date Tue, 03 Oct 2023 19:35:29 +0000
parents cbfcc480d61b
children
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
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53
737579209153 fpga/sniffer-pps: add LED indication of running SIM CLK
Mychaela Falconia <falcon@freecalypso.org>
parents: 52
diff changeset
1 VSRC= clk_check.v clk_edge.v pps_catcher.v reset_detect.v sniff_rx.v \
737579209153 fpga/sniffer-pps: add LED indication of running SIM CLK
Mychaela Falconia <falcon@freecalypso.org>
parents: 52
diff changeset
2 spenh_ctrl.v sync_inputs.v top.v uart_tx.v
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990ecafdddb4 fpga tree: move icestick.pcf to common subdirectory
Mychaela Falconia <falcon@freecalypso.org>
parents: 19
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3 PCF= ../common/icestick.pcf
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7db5fd6646df fpga/sniffer-basic: initial version
Mychaela Falconia <falcon@freecalypso.org>
parents:
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4 PROJ= fpga
7db5fd6646df fpga/sniffer-basic: initial version
Mychaela Falconia <falcon@freecalypso.org>
parents:
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5
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82da4b7835b7 FPGA Makefile: generate timing.rpt
Mychaela Falconia <falcon@freecalypso.org>
parents: 12
diff changeset
6 all: ${PROJ}.bin timing.rpt
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7db5fd6646df fpga/sniffer-basic: initial version
Mychaela Falconia <falcon@freecalypso.org>
parents:
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7
7db5fd6646df fpga/sniffer-basic: initial version
Mychaela Falconia <falcon@freecalypso.org>
parents:
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8 ${PROJ}.json: ${VSRC}
52
cbfcc480d61b fpga build: migrate to yosys-tee wrapper
Mychaela Falconia <falcon@freecalypso.org>
parents: 31
diff changeset
9 ../tools/yosys-tee top $@ synthesis.rpt ${VSRC}
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7db5fd6646df fpga/sniffer-basic: initial version
Mychaela Falconia <falcon@freecalypso.org>
parents:
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10
7db5fd6646df fpga/sniffer-basic: initial version
Mychaela Falconia <falcon@freecalypso.org>
parents:
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11 ${PROJ}.asc: ${PROJ}.json ${PCF}
7db5fd6646df fpga/sniffer-basic: initial version
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
12 nextpnr-ice40 --hx1k --package tq144 --asc $@ --pcf ${PCF} \
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d29dcfa78124 FPGA Makefile: generate pnr.rpt
Mychaela Falconia <falcon@freecalypso.org>
parents: 9
diff changeset
13 --json ${PROJ}.json -l pnr.rpt
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7db5fd6646df fpga/sniffer-basic: initial version
Mychaela Falconia <falcon@freecalypso.org>
parents:
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14
7db5fd6646df fpga/sniffer-basic: initial version
Mychaela Falconia <falcon@freecalypso.org>
parents:
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15 ${PROJ}.bin: ${PROJ}.asc
7db5fd6646df fpga/sniffer-basic: initial version
Mychaela Falconia <falcon@freecalypso.org>
parents:
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16 icepack $< $@
7db5fd6646df fpga/sniffer-basic: initial version
Mychaela Falconia <falcon@freecalypso.org>
parents:
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17
13
82da4b7835b7 FPGA Makefile: generate timing.rpt
Mychaela Falconia <falcon@freecalypso.org>
parents: 12
diff changeset
18 timing.rpt: ${PROJ}.asc
82da4b7835b7 FPGA Makefile: generate timing.rpt
Mychaela Falconia <falcon@freecalypso.org>
parents: 12
diff changeset
19 icetime -d hx1k -mtr $@ $<
82da4b7835b7 FPGA Makefile: generate timing.rpt
Mychaela Falconia <falcon@freecalypso.org>
parents: 12
diff changeset
20
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7db5fd6646df fpga/sniffer-basic: initial version
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
21 clean:
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e92ab75ce6a8 FPGA make clean: rm *.rpt too
Mychaela Falconia <falcon@freecalypso.org>
parents: 18
diff changeset
22 rm -f *.json *.asc *.bin *.rpt