FreeCalypso > hg > fc-sim-sniff

annotate fpga/sniffer-pps/Makefile @ 31:ab37fcb71744

Find changesets by keywords (author, files, the commit message), revision number or hash, or revset expression.
fpga/sniffer-pps: add actual F/D control
author Mychaela Falconia <falcon@freecalypso.org>
date Tue, 29 Aug 2023 21:22:37 +0000
parents 0f74428c177c
children cbfcc480d61b
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
rev   line source
31
ab37fcb71744 fpga/sniffer-pps: add actual F/D control
Mychaela Falconia <falcon@freecalypso.org>
parents: 28
diff changeset
1 VSRC= clk_edge.v pps_catcher.v reset_detect.v sniff_rx.v spenh_ctrl.v \
ab37fcb71744 fpga/sniffer-pps: add actual F/D control
Mychaela Falconia <falcon@freecalypso.org>
parents: 28
diff changeset
2 sync_inputs.v top.v uart_tx.v
27
990ecafdddb4 fpga tree: move icestick.pcf to common subdirectory
Mychaela Falconia <falcon@freecalypso.org>
parents: 19
diff changeset
3 PCF= ../common/icestick.pcf
6
7db5fd6646df fpga/sniffer-basic: initial version
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
4 PROJ= fpga
7db5fd6646df fpga/sniffer-basic: initial version
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
5
13
82da4b7835b7 FPGA Makefile: generate timing.rpt
Mychaela Falconia <falcon@freecalypso.org>
parents: 12
diff changeset
6 all: ${PROJ}.bin timing.rpt
6
7db5fd6646df fpga/sniffer-basic: initial version
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
7
7db5fd6646df fpga/sniffer-basic: initial version
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
8 ${PROJ}.json: ${VSRC}
18
af1a9732da1f FPGA build: include yosys-wrap in this repository
Mychaela Falconia <falcon@freecalypso.org>
parents: 13
diff changeset
9 ../tools/yosys-wrap top $@ ${VSRC} | tee synthesis.rpt
6
7db5fd6646df fpga/sniffer-basic: initial version
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
10
7db5fd6646df fpga/sniffer-basic: initial version
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
11 ${PROJ}.asc: ${PROJ}.json ${PCF}
7db5fd6646df fpga/sniffer-basic: initial version
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
12 nextpnr-ice40 --hx1k --package tq144 --asc $@ --pcf ${PCF} \
12
d29dcfa78124 FPGA Makefile: generate pnr.rpt
Mychaela Falconia <falcon@freecalypso.org>
parents: 9
diff changeset
13 --json ${PROJ}.json -l pnr.rpt
6
7db5fd6646df fpga/sniffer-basic: initial version
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
14
7db5fd6646df fpga/sniffer-basic: initial version
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
15 ${PROJ}.bin: ${PROJ}.asc
7db5fd6646df fpga/sniffer-basic: initial version
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
16 icepack $< $@
7db5fd6646df fpga/sniffer-basic: initial version
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
17
13
82da4b7835b7 FPGA Makefile: generate timing.rpt
Mychaela Falconia <falcon@freecalypso.org>
parents: 12
diff changeset
18 timing.rpt: ${PROJ}.asc
82da4b7835b7 FPGA Makefile: generate timing.rpt
Mychaela Falconia <falcon@freecalypso.org>
parents: 12
diff changeset
19 icetime -d hx1k -mtr $@ $<
82da4b7835b7 FPGA Makefile: generate timing.rpt
Mychaela Falconia <falcon@freecalypso.org>
parents: 12
diff changeset
20
6
7db5fd6646df fpga/sniffer-basic: initial version
Mychaela Falconia <falcon@freecalypso.org>
parents:
diff changeset
21 clean:
19
e92ab75ce6a8 FPGA make clean: rm *.rpt too
Mychaela Falconia <falcon@freecalypso.org>
parents: 18
diff changeset
22 rm -f *.json *.asc *.bin *.rpt