view fpga/sniffer-pps/Makefile @ 31:ab37fcb71744

fpga/sniffer-pps: add actual F/D control
author Mychaela Falconia <falcon@freecalypso.org>
date Tue, 29 Aug 2023 21:22:37 +0000
parents 0f74428c177c
children cbfcc480d61b
line wrap: on
line source

VSRC=	clk_edge.v pps_catcher.v reset_detect.v sniff_rx.v spenh_ctrl.v \
	sync_inputs.v top.v uart_tx.v
PCF=	../common/icestick.pcf
PROJ=	fpga

all:	${PROJ}.bin timing.rpt

${PROJ}.json:	${VSRC}
	../tools/yosys-wrap top $@ ${VSRC} | tee synthesis.rpt

${PROJ}.asc:	${PROJ}.json ${PCF}
	nextpnr-ice40 --hx1k --package tq144 --asc $@ --pcf ${PCF} \
		--json ${PROJ}.json -l pnr.rpt

${PROJ}.bin:	${PROJ}.asc
	icepack $< $@

timing.rpt:	${PROJ}.asc
	icetime -d hx1k -mtr $@ $<

clean:
	rm -f *.json *.asc *.bin *.rpt