FreeCalypso > hg > fc-sim-sniff

annotate fpga/sniffer-pps/Makefile @ 29:8be0b96b7c8d

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fpga: add top Makefile across projects
author Mychaela Falconia <falcon@freecalypso.org>
date Tue, 29 Aug 2023 20:35:51 +0000
parents 0f74428c177c
children ab37fcb71744
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
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0f74428c177c fpga/sniffer-pps: first version
Mychaela Falconia <falcon@freecalypso.org>
parents: 27
diff changeset
1 VSRC= clk_edge.v pps_catcher.v reset_detect.v sniff_rx.v sync_inputs.v top.v \
0f74428c177c fpga/sniffer-pps: first version
Mychaela Falconia <falcon@freecalypso.org>
parents: 27
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2 uart_tx.v
27
990ecafdddb4 fpga tree: move icestick.pcf to common subdirectory
Mychaela Falconia <falcon@freecalypso.org>
parents: 19
diff changeset
3 PCF= ../common/icestick.pcf
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7db5fd6646df fpga/sniffer-basic: initial version
Mychaela Falconia <falcon@freecalypso.org>
parents:
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4 PROJ= fpga
7db5fd6646df fpga/sniffer-basic: initial version
Mychaela Falconia <falcon@freecalypso.org>
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5
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82da4b7835b7 FPGA Makefile: generate timing.rpt
Mychaela Falconia <falcon@freecalypso.org>
parents: 12
diff changeset
6 all: ${PROJ}.bin timing.rpt
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7db5fd6646df fpga/sniffer-basic: initial version
Mychaela Falconia <falcon@freecalypso.org>
parents:
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7
7db5fd6646df fpga/sniffer-basic: initial version
Mychaela Falconia <falcon@freecalypso.org>
parents:
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8 ${PROJ}.json: ${VSRC}
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af1a9732da1f FPGA build: include yosys-wrap in this repository
Mychaela Falconia <falcon@freecalypso.org>
parents: 13
diff changeset
9 ../tools/yosys-wrap top $@ ${VSRC} | tee synthesis.rpt
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7db5fd6646df fpga/sniffer-basic: initial version
Mychaela Falconia <falcon@freecalypso.org>
parents:
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10
7db5fd6646df fpga/sniffer-basic: initial version
Mychaela Falconia <falcon@freecalypso.org>
parents:
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11 ${PROJ}.asc: ${PROJ}.json ${PCF}
7db5fd6646df fpga/sniffer-basic: initial version
Mychaela Falconia <falcon@freecalypso.org>
parents:
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12 nextpnr-ice40 --hx1k --package tq144 --asc $@ --pcf ${PCF} \
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d29dcfa78124 FPGA Makefile: generate pnr.rpt
Mychaela Falconia <falcon@freecalypso.org>
parents: 9
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13 --json ${PROJ}.json -l pnr.rpt
6
7db5fd6646df fpga/sniffer-basic: initial version
Mychaela Falconia <falcon@freecalypso.org>
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14
7db5fd6646df fpga/sniffer-basic: initial version
Mychaela Falconia <falcon@freecalypso.org>
parents:
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15 ${PROJ}.bin: ${PROJ}.asc
7db5fd6646df fpga/sniffer-basic: initial version
Mychaela Falconia <falcon@freecalypso.org>
parents:
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16 icepack $< $@
7db5fd6646df fpga/sniffer-basic: initial version
Mychaela Falconia <falcon@freecalypso.org>
parents:
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17
13
82da4b7835b7 FPGA Makefile: generate timing.rpt
Mychaela Falconia <falcon@freecalypso.org>
parents: 12
diff changeset
18 timing.rpt: ${PROJ}.asc
82da4b7835b7 FPGA Makefile: generate timing.rpt
Mychaela Falconia <falcon@freecalypso.org>
parents: 12
diff changeset
19 icetime -d hx1k -mtr $@ $<
82da4b7835b7 FPGA Makefile: generate timing.rpt
Mychaela Falconia <falcon@freecalypso.org>
parents: 12
diff changeset
20
6
7db5fd6646df fpga/sniffer-basic: initial version
Mychaela Falconia <falcon@freecalypso.org>
parents:
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21 clean:
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e92ab75ce6a8 FPGA make clean: rm *.rpt too
Mychaela Falconia <falcon@freecalypso.org>
parents: 18
diff changeset
22 rm -f *.json *.asc *.bin *.rpt