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fpga/sniffer-pps: add actual F/D control
author Mychaela Falconia <falcon@freecalypso.org>
date Tue, 29 Aug 2023 21:22:37 +0000
parents c03a882cc49e
children 695ca51e1564
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1 The first version of SIMtrace3 sniffer FPGA (the version in fpga/sniffer-basic,
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2 no PPS catcher, F/D=372 only for now) has been implemented, tested and proven
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3 working. It is an FPGA image for Lattice Icestick, an inexpensive off-the-shelf
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4 iCE40 FPGA board, and it implements the function of passive sniffing: receiving
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5 level-shifted SIM RST, CLK and I/O signals from the 74LVC4T3144 buffer and
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6 capturing all exchanges that happen on the SIM interface between a GSM ME or
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7 other interface device (ME/ID for short) and a SIM.
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9 Hardware architecture and FPGA design principle
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10 ===============================================
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12 The two principal components of the Icestick board are an iCE40HX1K FPGA and an
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13 FT2232H-based USB host interface. Our sniffer logic function in the FPGA
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14 operates principally as a byte forwarder from the ISO 7816-3 sniffer block to
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15 the FT2232H UART: every time the bus sniffer block captures a character (in ISO
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16 7816-3 terminology) being passed on the SIM electrical interface in either
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17 direction (the two directions of transmission are indistinguishable to a tap
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18 sniffer that does not actively participate in the protocol), the FPGA will
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19 forward this character to the connected host computer (by way of FT2232H UART)
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20 for further processing in software. The UART data line going from the FPGA to
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21 the FT2232H is the sole functional output from this FPGA, beyond debug outputs
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22 being added during logic development and troubleshooting. The other UART data
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23 line going the opposite direction (output from FT2232H) remains unused in this
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24 application, i.e., the host software application will only read/receive from the
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25 ttyUSBx FPGA device and won't send anything to it. All modem control lines on
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26 this UART interface likewise remain unused.
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28 Serial interface format
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29 =======================
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31 For every ISO 7816-3 character captured by the sniffer, two back-to-back UART
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32 bytes will be transferred from the FPGA to the host computer; more generally,
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33 the FPGA will only transmit pairs of back-to-back bytes on this UART and no
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34 singletons or other arrangements - thus the host receiver can always recover
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35 synchronization by dropping any partially received two-byte message (the first
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36 byte of an expected pair) during prolonged pauses. The FPGA will transmit the
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37 two back-to-back UART bytes as a single shift-out of 20 bits, conveying two
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38 bytes in 8N1 framing.
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40 Why are we turning every captured ISO 7816-3 character into a pair of bytes on
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41 our internal UART interface, why not simply forward it as a single byte? The
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42 reason is that we need to pass some additional bits beyond the 8 that comprise
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43 the ISO 7816-3 character payload; the additional bits which we need to pass are
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44 as follows:
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45
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46 - the received parity bit;
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47 - a flag indicating whether or not an error signal (ISO 7816-3 section 7.3)
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48 was seen;
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49 - additional flag bits communicating SIM RST assertion and negation events,
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50 as distinct from ISO 7816-3 characters;
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51 - an additional flag indicating an action of the integrated PPS catcher state
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52 machine, to be described later in this document.
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53
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54 Assertion or negation of SIM RST is the only other possible event (besides ISO
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55 7816-3 character capture, with or without attendant PPS catcher state machine
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56 action) that can cause the FPGA to send a byte-pair UART message to the host
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57 computer. One bit in the 16-bit message will distinguish between characters
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58 and RST events, another bit will indicate the state of RST at the time of the
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59 event (new RST for transitions, 1 for characters), and all other bits are
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60 meaningful only for characters.
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61
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62 Detailed serial interface format
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63 --------------------------------
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64
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65 Treating the two transmitted bytes as a single 16-bit word, with the least
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66 significant 8 bits transmitted first (matching the transmission order of bits
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67 within a byte), the 16 bits of this word are assigned as follows:
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68
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69 Bit 15: set to 0 if this message signals ISO 7816-3 character reception or 1 if
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70 it signals a change of state in the RST line.
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71
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72 Bit 14: new state of RST in the case of RST state change messages; should always
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73 be 1 in character Rx messages.
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74
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75 Bits [13:11]: currently unused and set to 0.
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76
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77 The remaining bits are valid only in character Rx messages:
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78
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79 Bit 10: set to 1 if the error signal of ISO 7816-3 section 7.3 was detected,
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80 0 otherwise.
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81
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82 Bit 9: sampled line value at the midpoint of the start bit, should be 0 in a
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83 properly working system.
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84
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85 Bit 8: received parity bit;
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86
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87 Bits [7:0]: payload bits of the received character.
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88
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89 UART baud rate
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90 ==============
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91
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92 The baud rate on the UART interface between the FPGA and the FT2232H converter
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93 is 3000000 bps. This high (and very non-RS232-standard) UART baud rate was
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94 chosen for the following reasons:
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95
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96 * Our UART interface is totally private, going nowhere but the on-board FT2232H,
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97 thus it doesn't matter if the baud rate is standard-ish or totally
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98 non-standard.
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99
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100 * No cables of any kind are used, instead the UART interface is confined to
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101 short PCB traces running between the FPGA and the FTDI chip on the same board
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102 - hence high baud rates are not a problem.
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103
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104 * Our UART baud rate needs to be high enough to provide good margin, despite
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105 our 2x expansion, at the highest possible effective bps rate on the SIM
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106 interface, meaning the highest possible SIM CLK frequency and the most
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107 aggressive F/D ratio. The combination of SIM CLK at 5 MHz, F=512 and D=64
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108 corresponds to 625000 bps effective on the SIM interface; running our UART at
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109 3 Mbps provides sufficient margin.
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110
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111 Clocking design
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112 ===============
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113
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114 The FPGA on the Icestick board receives a 12 MHz clock input. Our original
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115 plan was to use the FPGA's on-chip PLL to multiply this clock by 4, producing a
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116 48 MHz system clock - however, this plan has been shelved for now, and our
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117 current sniffer-basic design uses the 12 MHz clock directly as its system clock.
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118
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119 The 3 inputs to the FPGA coming from the SIM electrical sniffer (buffered and
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120 level-shifted SIM RST, CLK and I/O lines) pass through two cascaded DFFs,
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121 bringing them into our internal clock domain. The delay added by these cascaded
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122 DFFs is not a concern: we are a passive sniffer without any output back to the
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123 SIM interface, and all 3 signal inputs will be subject to the same delay.
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124
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125 As stated in the previous section, the baud rate on the UART interface between
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126 the FPGA and the FT2232H converter is 3000000 bps. The UART output block in
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127 the FPGA uses a simple /4 divider from CLK12 (board-level 12 MHz clock input)
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128 to time its output bits; the original intent was to use a /16 divider from
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129 48 MHz SYSCLK.
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130
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131 ISO 7816-3 sniffer block
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132 ========================
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133
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134 Our ISO 7816-3 receiver will trigger on the falling edge of the I/O line. Once
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135 it detects a high-to-low transition on the SYSCLK-synchronized SIM_IO input, it
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136 will start counting SIM CLK cycles - we are arbitrarily choosing low-to-high
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137 transition of SYSCLK-synchronized SIM_CLK input as the trigger point. (This
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138 choice is arbitrary because per the spec there is no defined phase relation
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139 between SIM CLK and SIM I/O transitions.) Our ISO 7816-3 receiver will need to
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140 know how many SIM CLK cycles constitute one etu - or more precisely, our
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141 sniffing receiver needs to know how many SIM CLK cycles constitute 0.5 etu,
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142 1 etu and 1.5 etu, in order to locate various needed sampling points relative
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143 to the instant at which SIM_IO was initially sampled low.
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144
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145 The initial version of our sniffer gateware (the version in fpga/sniffer-basic)
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146 omits the PPS catcher block, hence the just-described etu durations are
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147 currently fixed to F/D=372 default values.
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148
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149 Direct and inverse coding conventions
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150 =====================================
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151
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152 Only the card and not the interface device (ISO 7816-3 terminology) determines
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153 which coding convention is used, direct or inverse. So far we (FreeCalypso)
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154 have not yet encountered a real-life SIM that uses the inverse convention, only
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155 the direct convention kind. In the sniffer function of SIMtrace-ice, we are
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156 going to keep our FPGA gateware simple in this regard and punt all inverse
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157 convention handling to the software application on the host computer: the FPGA
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158 passes the 9 received bits (8 data bits and 1 parity bit) to the 16-bit UART
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159 message as-is, without inverting or reordering them.
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160
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161 Integrated PPS catcher
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162 ======================
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163
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164 The logic described so far and implemented in the sniffer-basic version will be
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165 sufficient to capture all exchanges on the SIM interface between ME/ID and a SIM
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166 *if* the etu-defining F/D ratio is never switched from the basic default of 372.
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167 However, given that most SIM cards of interest to us (our own FCSIM1, as well as
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168 SIMs issued by various commercial operators) support Fi=512 Di=8 or higher, and
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169 given that even very classic implementations of GSM ME (including our dear
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170 Calypso) support this F=512 D=8 speed enhancement mode endorsed by GSM 11.11
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171 spec, many real-life ME/ID-to-SIM sessions (which we would like to sniff and
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172 trace) will include a PPS exchange switching to a smaller number of SIM CLK
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173 cycles per etu.
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174
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175 The main difficulty with capturing SIM interface sessions that use speed
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176 enhancement is as follows: in order for the session capture to be complete,
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177 without any lost bits, the sniffing receiver's knowledge of how many SIM CLK
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178 cycles constitute an etu needs to change to the new value at exactly the
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179 correct moment in time, which is the moment immediately after the last byte
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180 (PCK) of the SIM's PPS response passes across the wire. If we were to rely on
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181 host software to decode all byte exchanges up to this point (ATR from the SIM,
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182 PPS request from ME/ID, then PPS response) and command the FPGA (UART in the
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183 other direction, or a modem control line) to switch the etu counters (the
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184 0.5 etu, 1 etu and 1.5 etu counters mentioned above), we stand very little
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185 chance of getting this command to the FPGA in time, before ME/ID starts
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186 transmitting its next command to the SIM using the new etu definition.
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187
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188 The Mother's proposed solution is to embed a PPS catcher state machine in the
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189 sniffer FPGA. This state machine will be set to its initial state upon the
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190 session-opening low-to-high transition on the RST line, and it will look at
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191 every ISO 7816-3 character received by the sniffer. The machine will need to
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192 step through the following states between this starting point and the final
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193 action of changing the half-etu count register:
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194
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195 * As the ATR bytes are transferred, the state machine will need to understand
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196 enough of ATR format to know which byte constitutes the end of ATR. A fatal
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197 error in ATR real-time parsing (if the first byte is anything other than
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198 8'h3B) will put the machine into its inactive state for the remainder of the
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199 session until next reset.
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200
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201 * If the byte following ATR is 8'hFF, the machine will proceed into PPS request
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202 real-time parsing state. If this byte equals any other value, go to the
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203 inactive state for the remainder of the session.
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204
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205 * In the PPS request real-time parsing series of states, the state machine will
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206 need to catch the PPS0 byte and based on this byte, figure out how many bytes
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207 it needs to skip.
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208
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209 * Following the PPS request, the machine will need to real-time-parse the PPS
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210 response. Any invalid conditions will take it to the inactive state; however,
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211 if the PPS exchange is valid, the machine will need to capture the PPS1 byte
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212 and then step through states until the final PCK byte of the PPS response.
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213
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214 * Upon receiving that last PCK byte after all prior bytes following the expected
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215 protocol, effect the etu counter change. Either way, the inactive state is
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216 entered at this point, and the state machine will take no further action for
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217 the remainder of the session.
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218
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219 This state machine is of course going to be very complicated, as evident from
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220 the functional requirements listed above. The first version of SIMtrace-ice
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221 sniffer FPGA omits this block altogether, and we will get the rest of the
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222 system working for ME/ID-to-SIM sessions that stick with F/D=372 - a good test
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223 configuration would be to use a FreeCalypso GSM ME, with SIM speed enhancement
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224 disabled via AT@SPENH=0. Then we shall embark on implementing this proposed
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225 PPS catcher state machine.
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226
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227 The addition of this PPS catcher state machine may increase the complexity of
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228 our logic beyond the capacity of the iCE40HX1K FPGA on the Icestick board. If
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229 we run into this problem, we'll have to look for a board with a bigger FPGA -
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230 but we'll try to fit into the Icestick first.