FreeCalypso > hg > fc-sim-sniff

annotate fpga/sniffer-basic/Makefile @ 25:c03a882cc49e

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doc/Sniffer-FPGA-design: update for working status
author Mychaela Falconia <falcon@freecalypso.org>
date Tue, 29 Aug 2023 06:37:58 +0000
parents e92ab75ce6a8
children 990ecafdddb4
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
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7db5fd6646df fpga/sniffer-basic: initial version
Mychaela Falconia <falcon@freecalypso.org>
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1 VSRC= clk_edge.v reset_detect.v sniff_rx.v sync_inputs.v top.v uart_tx.v
7db5fd6646df fpga/sniffer-basic: initial version
Mychaela Falconia <falcon@freecalypso.org>
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2 PCF= icestick.pcf
7db5fd6646df fpga/sniffer-basic: initial version
Mychaela Falconia <falcon@freecalypso.org>
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3 PROJ= fpga
7db5fd6646df fpga/sniffer-basic: initial version
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82da4b7835b7 FPGA Makefile: generate timing.rpt
Mychaela Falconia <falcon@freecalypso.org>
parents: 12
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5 all: ${PROJ}.bin timing.rpt
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7db5fd6646df fpga/sniffer-basic: initial version
Mychaela Falconia <falcon@freecalypso.org>
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7db5fd6646df fpga/sniffer-basic: initial version
Mychaela Falconia <falcon@freecalypso.org>
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7 ${PROJ}.json: ${VSRC}
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af1a9732da1f FPGA build: include yosys-wrap in this repository
Mychaela Falconia <falcon@freecalypso.org>
parents: 13
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8 ../tools/yosys-wrap top $@ ${VSRC} | tee synthesis.rpt
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7db5fd6646df fpga/sniffer-basic: initial version
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7db5fd6646df fpga/sniffer-basic: initial version
Mychaela Falconia <falcon@freecalypso.org>
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10 ${PROJ}.asc: ${PROJ}.json ${PCF}
7db5fd6646df fpga/sniffer-basic: initial version
Mychaela Falconia <falcon@freecalypso.org>
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11 nextpnr-ice40 --hx1k --package tq144 --asc $@ --pcf ${PCF} \
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d29dcfa78124 FPGA Makefile: generate pnr.rpt
Mychaela Falconia <falcon@freecalypso.org>
parents: 9
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12 --json ${PROJ}.json -l pnr.rpt
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7db5fd6646df fpga/sniffer-basic: initial version
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7db5fd6646df fpga/sniffer-basic: initial version
Mychaela Falconia <falcon@freecalypso.org>
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14 ${PROJ}.bin: ${PROJ}.asc
7db5fd6646df fpga/sniffer-basic: initial version
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15 icepack $< $@
7db5fd6646df fpga/sniffer-basic: initial version
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82da4b7835b7 FPGA Makefile: generate timing.rpt
Mychaela Falconia <falcon@freecalypso.org>
parents: 12
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17 timing.rpt: ${PROJ}.asc
82da4b7835b7 FPGA Makefile: generate timing.rpt
Mychaela Falconia <falcon@freecalypso.org>
parents: 12
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18 icetime -d hx1k -mtr $@ $<
82da4b7835b7 FPGA Makefile: generate timing.rpt
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parents: 12
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7db5fd6646df fpga/sniffer-basic: initial version
Mychaela Falconia <falcon@freecalypso.org>
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20 clean:
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e92ab75ce6a8 FPGA make clean: rm *.rpt too
Mychaela Falconia <falcon@freecalypso.org>
parents: 18
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21 rm -f *.json *.asc *.bin *.rpt