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doc/Sniffing-hw-setup: mv-sniffer is here
author Mychaela Falconia <falcon@freecalypso.org>
date Wed, 04 Oct 2023 05:55:09 +0000
parents 8a3003860cf8
children
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1 The hardware setup for SIM interface sniffing with FC SIMsniff consists of the
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2 following components:
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4 * The same SIMtrace FPC cables (going from a SIM socket to the 6-pin FPC
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5 connector) that were originally developed for SIMtrace1/2 and are sold by
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6 Sysmocom;
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8 * An off-the-shelf Lattice Icestick FPGA board (sold by Digi-Key, for example)
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9 that has been outfitted with header pins: the board ships with empty PTHs
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10 (plated through holes) at J1, hence a small soldering job is required to
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11 populate this header;
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13 * Some in-between components described below.
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15 For the in-between components of the last bullet point above, there are 3
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16 possibilities, each described in its own section below.
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18 HW setup version 1
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19 ==================
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21 (works today)
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23 In this solution there are two little ad hoc boards sitting between the SIMtrace
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24 FPC cable and the Icestick board:
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26 * sim-fpc-pasv board produced in the fall of 2022
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27 * mv-sniffer board produced in the fall of 2023
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29 The first board (sim-fpc-pasv) passively interconnects an FPC connector for
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30 SIMtrace cables, a physical SIM socket and a bunch of 2.54 mm header pins,
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31 bringing out all lines of the SIM-ME electrical interface. This board was
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32 originally produced a year ago for the purpose of observing SIM voltages and
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33 clocks with an oscilloscope. The second board adds one active component:
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34 Nexperia 74LVC4T3144 dual supply logic voltage level translator IC, powered
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35 from SIM_VCC on its A side and from Icestick board +3.3V rail on its B side.
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37 The buffer IC receives (sniffs) the SIM-ME electrical interface at whichever
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38 voltage the ME puts out (everything from 1.8V to 5V is accepted) and puts out
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39 the same signals at the fixed logic voltage level needed by the FPGA on the
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40 Icestick; the FPGA then sniffs the ISO 7816-3 protocol just above the electrical
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41 level.
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43 Wire assignments for this HW setup
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44 ----------------------------------
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46 A 6-wire ribbon cable, cut from a standard multicolor ribbon cable spool and
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47 outfitted with custom crimped connectors, is used to make the connection
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48 between sim-fpc-pasv and mv-sniffer boards. Wire color assignments in this
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49 ad hoc connection cable are:
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51 Wire SIM interface pin
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52 ---------------------------------
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53 brown VCC
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54 red RST
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55 orange CLK
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56 yellow GND
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57 green GND
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58 blue I/O
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59
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60 HW setup version 2
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61 ==================
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63 (a little more distant, but will be needed before wider spread)
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65 The solution with separate sim-fpc-pasv and mv-sniffer boards is quite
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66 inconvenient because of the number of pieces required - clutter on the lab
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67 bench - plus poor electrical design with jumper wires between the two boards
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68 extending the electrical length of the SIM bus before the LVC buffer. In the
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69 fully polished version of FC SIMsniff, these two adapter boards will need to be
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70 combined into one. The final FreeCalypso SIMsniff pod is expected to be a
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71 single board (still very simple and low cost) featuring the following
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72 components:
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74 1) SIMtrace FPC connector
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75 2) SIM socket
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76 3) 74LVC4T3144 buffer IC
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77 4) SIM bus solidly connected between components 1, 2 and 3
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78 5) A header for FPGA board connection, wired to the 'B' side of component 3
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80 HW setup version 0 (historical)
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81 ===============================
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82
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83 In the beginning of FC SIMsniff project, there was no new custom hardware - but
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84 we did have our sim-fpc-pasv board from a year ago, and we got the Icestick
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85 board outfitted with header pins. Our first hw setup thus consisted of jumper
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86 wires connecting from FPGA I/O pins (plus Icestick GND) directly to SIM bus pins
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87 on the sim-fpc-pasv adapter.
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88
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89 This hw setup could not be used for any real SIM-ME sniffing: a class A (5V) ME
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90 would destroy the FPGA (grossly exceeds Absolute Maximum Ratings), while class C
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91 (1.8V) operation produced by all newer ME (from Calypso+Iota onward) cannot be
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92 picked up directly by the FPGA as the high logic level falls right between
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93 Vil_max and Vih_min, causing the FPGA to receive garbage. However, this setup
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94 worked with FCDEV3B forced into class B operation, and was used to develop our
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95 FPGA logic and prove it working before the arrival of mv-sniffer board.