FreeCalypso > hg > fc-sim-sniff
diff fpga/tools/yosys-tee @ 52:cbfcc480d61b
fpga build: migrate to yosys-tee wrapper
author | Mychaela Falconia <falcon@freecalypso.org> |
---|---|
date | Tue, 03 Oct 2023 18:17:58 +0000 |
parents | fpga/tools/yosys-wrap@af1a9732da1f |
children |
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--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/fpga/tools/yosys-tee Tue Oct 03 18:17:58 2023 +0000 @@ -0,0 +1,27 @@ +#!/bin/sh + +if [ $# -lt 4 ] +then + echo "usage: $0 top-module json-output report-out verilog-src..." 1>&2 + exit 1 +fi + +top="$1" +json="$2" +report="$3" + +shift +shift +shift + +rm -f "$json" +yosys -p "synth_ice40 -top $top -json $json" "$@" | tee "$report" + +if [ -f "$json" ] +then + echo "$json created, declaring success" + exit 0 +else + echo "$json NOT created, declaring error" + exit 1 +fi