FreeCalypso > hg > fc-sim-sniff
annotate fpga/tools/yosys-tee @ 52:cbfcc480d61b
fpga build: migrate to yosys-tee wrapper
author | Mychaela Falconia <falcon@freecalypso.org> |
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date | Tue, 03 Oct 2023 18:17:58 +0000 |
parents | fpga/tools/yosys-wrap@af1a9732da1f |
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FPGA build: include yosys-wrap in this repository
Mychaela Falconia <falcon@freecalypso.org>
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1 #!/bin/sh |
af1a9732da1f
FPGA build: include yosys-wrap in this repository
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2 |
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fpga build: migrate to yosys-tee wrapper
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3 if [ $# -lt 4 ] |
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4 then |
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5 echo "usage: $0 top-module json-output report-out verilog-src..." 1>&2 |
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Mychaela Falconia <falcon@freecalypso.org>
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6 exit 1 |
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Mychaela Falconia <falcon@freecalypso.org>
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7 fi |
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Mychaela Falconia <falcon@freecalypso.org>
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8 |
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FPGA build: include yosys-wrap in this repository
Mychaela Falconia <falcon@freecalypso.org>
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9 top="$1" |
af1a9732da1f
FPGA build: include yosys-wrap in this repository
Mychaela Falconia <falcon@freecalypso.org>
parents:
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10 json="$2" |
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fpga build: migrate to yosys-tee wrapper
Mychaela Falconia <falcon@freecalypso.org>
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11 report="$3" |
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Mychaela Falconia <falcon@freecalypso.org>
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12 |
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13 shift |
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14 shift |
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15 shift |
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16 |
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17 rm -f "$json" |
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18 yosys -p "synth_ice40 -top $top -json $json" "$@" | tee "$report" |
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Mychaela Falconia <falcon@freecalypso.org>
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19 |
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FPGA build: include yosys-wrap in this repository
Mychaela Falconia <falcon@freecalypso.org>
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20 if [ -f "$json" ] |
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Mychaela Falconia <falcon@freecalypso.org>
parents:
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21 then |
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22 echo "$json created, declaring success" |
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23 exit 0 |
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24 else |
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25 echo "$json NOT created, declaring error" |
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Mychaela Falconia <falcon@freecalypso.org>
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26 exit 1 |
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Mychaela Falconia <falcon@freecalypso.org>
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27 fi |