FreeCalypso > hg > fc-sim-sniff

changeset 31:ab37fcb71744

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fpga/sniffer-pps: add actual F/D control
author Mychaela Falconia <falcon@freecalypso.org>
date Tue, 29 Aug 2023 21:22:37 +0000
parents dc99c9962aed
children fb9c03515832
files fpga/sniffer-pps/Makefile fpga/sniffer-pps/sniff_rx.v fpga/sniffer-pps/spenh_ctrl.v fpga/sniffer-pps/top.v
diffstat 4 files changed, 84 insertions(+), 10 deletions(-) [+]
line wrap: on
line diff
--- a/fpga/sniffer-pps/Makefile	Tue Aug 29 20:36:34 2023 +0000
+++ b/fpga/sniffer-pps/Makefile	Tue Aug 29 21:22:37 2023 +0000
@@ -1,5 +1,5 @@
-VSRC=	clk_edge.v pps_catcher.v reset_detect.v sniff_rx.v sync_inputs.v top.v \
-	uart_tx.v
+VSRC=	clk_edge.v pps_catcher.v reset_detect.v sniff_rx.v spenh_ctrl.v \
+	sync_inputs.v top.v uart_tx.v
 PCF=	../common/icestick.pcf
 PROJ=	fpga
 
--- a/fpga/sniffer-pps/sniff_rx.v	Tue Aug 29 20:36:34 2023 +0000
+++ b/fpga/sniffer-pps/sniff_rx.v	Tue Aug 29 21:22:37 2023 +0000
@@ -3,24 +3,61 @@
  */
 
 module sniff_rx (IntClk, SIM_RST_sync, SIM_CLK_sync, SIM_IO_sync,
-		 Rx_strobe, Rx_error, Rx_char, Rx_start_bit, Rx_parity_bit);
+		 Rx_strobe, Rx_error, Rx_char, Rx_start_bit, Rx_parity_bit,
+		 speed_enh_mode, speed_enh_mult);
 
 input IntClk;
 input SIM_RST_sync, SIM_CLK_sync, SIM_IO_sync;
 output Rx_strobe, Rx_error;
 output [7:0] Rx_char;
 output Rx_start_bit, Rx_parity_bit;
+input speed_enh_mode;
+input [1:0] speed_enh_mult;
 
 wire SIM_CLK_edge;
 
 clk_edge clk_edge (IntClk, SIM_CLK_sync, SIM_CLK_edge);
 
-wire [9:0] etu_0p5, etu_1p0, etu_1p5;
+reg [9:0] etu_0p5, etu_1p0, etu_1p5;	/* combinational */
 
-/* Fi/Di=372 only for now */
-assign etu_0p5 = 10'd185;
-assign etu_1p0 = 10'd371;
-assign etu_1p5 = 10'd557;
+always @*
+	casez ({speed_enh_mode,speed_enh_mult})
+		3'b0??:
+		    begin
+			/* F/D = 372 */
+			etu_0p5 = 10'd185;
+			etu_1p0 = 10'd371;
+			etu_1p5 = 10'd557;
+		    end
+		3'b100:
+		    begin
+			/* F/D = 64 */
+			etu_0p5 = 10'd31;
+			etu_1p0 = 10'd63;
+			etu_1p5 = 10'd95;
+		    end
+		3'b101:
+		    begin
+			/* F/D = 32 */
+			etu_0p5 = 10'd15;
+			etu_1p0 = 10'd31;
+			etu_1p5 = 10'd47;
+		    end
+		3'b110:
+		    begin
+			/* F/D = 16 */
+			etu_0p5 = 10'd7;
+			etu_1p0 = 10'd15;
+			etu_1p5 = 10'd23;
+		    end
+		3'b111:
+		    begin
+			/* F/D = 8 */
+			etu_0p5 = 10'd3;
+			etu_1p0 = 10'd7;
+			etu_1p5 = 10'd11;
+		    end
+	endcase
 
 reg rx_active;
 reg [9:0] clk_count;
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/fpga/sniffer-pps/spenh_ctrl.v	Tue Aug 29 21:22:37 2023 +0000
@@ -0,0 +1,29 @@
+/*
+ * This module implements speed enhancement control based on signals
+ * from the PPS catcher block.
+ */
+
+module spenh_ctrl (IntClk, SIM_RST_sync, Rx_strobe, Rx_char,
+		   pos_PPS_resp_PPS1, pos_PPS_resp_PCK,
+		   speed_enh_mode, speed_enh_mult);
+
+input IntClk;
+input SIM_RST_sync;
+input Rx_strobe;
+input [7:0] Rx_char;
+input pos_PPS_resp_PPS1, pos_PPS_resp_PCK;
+
+output reg speed_enh_mode;
+output reg [1:0] speed_enh_mult;
+
+always @(posedge IntClk)
+	if (!SIM_RST_sync)
+		speed_enh_mode <= 1'b0;
+	else if (Rx_strobe && pos_PPS_resp_PCK)
+		speed_enh_mode <= 1'b1;
+
+always @(posedge IntClk)
+	if (Rx_strobe && pos_PPS_resp_PPS1)
+		speed_enh_mult <= Rx_char[1:0];
+
+endmodule
--- a/fpga/sniffer-pps/top.v	Tue Aug 29 20:36:34 2023 +0000
+++ b/fpga/sniffer-pps/top.v	Tue Aug 29 21:22:37 2023 +0000
@@ -24,8 +24,12 @@
 wire [7:0] Rx_char;
 wire Rx_start_bit, Rx_parity_bit;
 
+wire speed_enh_mode;
+wire [1:0] speed_enh_mult;
+
 sniff_rx sniff_rx (CLK12, SIM_RST_sync, SIM_CLK_sync, SIM_IO_sync,
-		   Rx_strobe, Rx_error, Rx_char, Rx_start_bit, Rx_parity_bit);
+		   Rx_strobe, Rx_error, Rx_char, Rx_start_bit, Rx_parity_bit,
+		   speed_enh_mode, speed_enh_mult);
 
 /* PPS catcher */
 
@@ -34,6 +38,10 @@
 pps_catcher pps (CLK12, SIM_RST_sync, Rx_strobe, Rx_char,
 		 pos_PPS_resp_PPS1, pos_PPS_resp_PCK);
 
+spenh_ctrl spenh (CLK12, SIM_RST_sync, Rx_strobe, Rx_char,
+		  pos_PPS_resp_PPS1, pos_PPS_resp_PCK,
+		  speed_enh_mode, speed_enh_mult);
+
 /* explicit detection of RST transitions */
 
 wire SIM_RST_toggle;
@@ -46,7 +54,7 @@
 wire [15:0] Tx_data;
 
 assign Tx_trigger = Rx_strobe | SIM_RST_toggle;
-assign Tx_data = {SIM_RST_toggle,SIM_RST_sync,1'b0,
+assign Tx_data = {SIM_RST_toggle,SIM_RST_sync,speed_enh_mode,
 		  pos_PPS_resp_PCK,pos_PPS_resp_PPS1,
 		  Rx_error,Rx_start_bit,Rx_parity_bit,Rx_char};