FreeCalypso > hg > fc-sim-sniff
changeset 18:af1a9732da1f
FPGA build: include yosys-wrap in this repository
| author | Mychaela Falconia <falcon@freecalypso.org> |
|---|---|
| date | Mon, 21 Aug 2023 19:25:35 +0000 |
| parents | 41e6026e5d1a |
| children | e92ab75ce6a8 |
| files | fpga/sniffer-basic/Makefile fpga/tools/yosys-wrap |
| diffstat | 2 files changed, 26 insertions(+), 1 deletions(-) [+] |
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--- a/fpga/sniffer-basic/Makefile Mon Aug 21 06:50:55 2023 +0000 +++ b/fpga/sniffer-basic/Makefile Mon Aug 21 19:25:35 2023 +0000 @@ -5,7 +5,7 @@ all: ${PROJ}.bin timing.rpt ${PROJ}.json: ${VSRC} - yosys-wrap top $@ ${VSRC} | tee synthesis.rpt + ../tools/yosys-wrap top $@ ${VSRC} | tee synthesis.rpt ${PROJ}.asc: ${PROJ}.json ${PCF} nextpnr-ice40 --hx1k --package tq144 --asc $@ --pcf ${PCF} \
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/fpga/tools/yosys-wrap Mon Aug 21 19:25:35 2023 +0000 @@ -0,0 +1,25 @@ +#!/bin/sh + +if [ $# -lt 3 ] +then + echo "usage: $0 top-module json-output verilog-src..." 1>&2 + exit 1 +fi + +top="$1" +json="$2" + +shift +shift + +rm -f "$json" +yosys -p "synth_ice40 -top $top -json $json" "$@" + +if [ -f "$json" ] +then + echo "$json created, declaring success" + exit 0 +else + echo "$json NOT created, declaring error" + exit 1 +fi