VSRC=	clk_edge.v reset_detect.v sniff_rx.v sync_inputs.v top.v uart_tx.v
PCF=	icestick.pcf
PROJ=	fpga

all:	${PROJ}.bin timing.rpt

${PROJ}.json:	${VSRC}
	../tools/yosys-wrap top $@ ${VSRC} | tee synthesis.rpt

${PROJ}.asc:	${PROJ}.json ${PCF}
	nextpnr-ice40 --hx1k --package tq144 --asc $@ --pcf ${PCF} \
		--json ${PROJ}.json -l pnr.rpt

${PROJ}.bin:	${PROJ}.asc
	icepack $< $@

timing.rpt:	${PROJ}.asc
	icetime -d hx1k -mtr $@ $<

clean:
	rm -f *.json *.asc *.bin