FreeCalypso > hg > fc-small-hw
annotate lunalcd2/src/Makefile @ 62:907bff95244d
lunalcd2/src/Makefile: generate elements.pcb
author | Mychaela Falconia <falcon@freecalypso.org> |
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date | Fri, 25 Jun 2021 19:11:21 +0000 |
parents | df8f40386c0b |
children | 000411b39576 |
rev | line source |
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lunalcd2: structural Verilog source captured
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1 VSRCS= vsrc/MAX1916.v vsrc/bl_current_sink.v vsrc/board.v \ |
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2 vsrc/current_select.v vsrc/lcd_module.v |
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lunalcd2/src/Makefile: generate pcb-netlist.txt
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3 NETS= sverp.unet bound.unet pcb-netlist.txt |
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4 |
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lunalcd2/src/Makefile: generate elements.pcb
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5 all: ${NETS} elements.pcb |
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6 |
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7 sverp.unet: ${VSRCS} primitives Makefile |
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8 ueda-sverp -o $@ ${VSRCS} |
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9 |
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10 bound.unet: MCL sverp.unet |
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11 unet-bind -c sverp.unet $@ |
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12 |
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lunalcd2/src/Makefile: generate pcb-netlist.txt
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13 pcb-netlist.txt: bound.unet |
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lunalcd2/src/Makefile: generate pcb-netlist.txt
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14 unet2pcb bound.unet $@ |
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lunalcd2/src/Makefile: generate pcb-netlist.txt
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lunalcd2/src/Makefile: generate elements.pcb
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16 elements.pcb: MCL |
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lunalcd2/src/Makefile: generate elements.pcb
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17 ueda-getfps -ch | ueda-runm4 > $@ |
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lunalcd2/src/Makefile: generate elements.pcb
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parents:
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18 |
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19 clean: |
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20 rm -f *.unet *.txt *.csv errs elements.pcb |