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annotate fpga/sniffer-pps/top.v @ 31:ab37fcb71744

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fpga/sniffer-pps: add actual F/D control
author Mychaela Falconia <falcon@freecalypso.org>
date Tue, 29 Aug 2023 21:22:37 +0000
parents dc99c9962aed
children 737579209153
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1 module top (CLK12, LED1, LED2, LED3, LED4, LED5, UART_TxD, UART_RxD, UART_RTS,
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2 UART_CTS, UART_DTR, UART_DSR, UART_DCD, SIM_RST_in, SIM_CLK_in,
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3 SIM_IO_in, SIM_IO_out);
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5 input CLK12;
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6 output LED1, LED2, LED3, LED4, LED5;
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8 input UART_TxD, UART_RTS, UART_DTR;
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9 output UART_RxD, UART_CTS, UART_DSR, UART_DCD;
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11 input SIM_RST_in, SIM_CLK_in, SIM_IO_in;
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12 output SIM_IO_out;
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14 /* input synchronizers */
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16 wire SIM_RST_sync, SIM_CLK_sync, SIM_IO_sync;
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18 sync_inputs sync (CLK12, SIM_RST_in, SIM_RST_sync, SIM_CLK_in, SIM_CLK_sync,
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19 SIM_IO_in, SIM_IO_sync);
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21 /* character receiver */
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23 wire Rx_strobe, Rx_error;
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24 wire [7:0] Rx_char;
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25 wire Rx_start_bit, Rx_parity_bit;
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27 wire speed_enh_mode;
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28 wire [1:0] speed_enh_mult;
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30 sniff_rx sniff_rx (CLK12, SIM_RST_sync, SIM_CLK_sync, SIM_IO_sync,
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31 Rx_strobe, Rx_error, Rx_char, Rx_start_bit, Rx_parity_bit,
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32 speed_enh_mode, speed_enh_mult);
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34 /* PPS catcher */
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36 wire pos_PPS_resp_PPS1, pos_PPS_resp_PCK;
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38 pps_catcher pps (CLK12, SIM_RST_sync, Rx_strobe, Rx_char,
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39 pos_PPS_resp_PPS1, pos_PPS_resp_PCK);
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41 spenh_ctrl spenh (CLK12, SIM_RST_sync, Rx_strobe, Rx_char,
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42 pos_PPS_resp_PPS1, pos_PPS_resp_PCK,
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43 speed_enh_mode, speed_enh_mult);
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45 /* explicit detection of RST transitions */
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47 wire SIM_RST_toggle;
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49 reset_detect reset_detect (CLK12, SIM_RST_sync, SIM_RST_toggle);
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51 /* output to the host */
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53 wire Tx_trigger;
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54 wire [15:0] Tx_data;
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56 assign Tx_trigger = Rx_strobe | SIM_RST_toggle;
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57 assign Tx_data = {SIM_RST_toggle,SIM_RST_sync,speed_enh_mode,
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58 pos_PPS_resp_PCK,pos_PPS_resp_PPS1,
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59 Rx_error,Rx_start_bit,Rx_parity_bit,Rx_char};
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61 uart_tx uart_tx (CLK12, Tx_trigger, Tx_data, UART_RxD);
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63 /* UART modem control outputs: unused */
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65 assign UART_CTS = 1'b1;
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66 assign UART_DSR = 1'b0;
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67 assign UART_DCD = 1'b0;
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69 /* board LEDs */
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71 assign LED1 = 1'b1;
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72 assign LED2 = 1'b0;
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73 assign LED3 = 1'b1;
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74 assign LED4 = 1'b0;
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75 assign LED5 = SIM_RST_in;
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77 /* SIM_IO_out dummy: if someone mistakenly connects an Icestick board with
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78 * this FPGA image in it to a cardem pod instead of the sniffing one,
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79 * we ensure that the 74LVC1G07 OD buffer remains off by feeding logic HIGH
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80 * to this buffer.
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81 */
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83 assign SIM_IO_out = 1'b1;
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85 endmodule